Abstract: Intelligent prediction of critical sections is implemented using a method comprising updating a critical section estimator based on historical analysis of atomic/store instruction pairs during runtime and performing lock elision when the critical section estimator indicates that the atomic/store instruction pairs define a critical section.

Abstract: A heat spreader apparatus for cooling an electronic component and method of attachment. The heat spreader comprises a flexible wall that partially conforms to a non-matching mating surface of the component when pressure is applied to the surface of the flexible wall that is opposite the component. The pressure may be maintained against the flexible wall during use, or released once the flexible wall is maintained in its conforming location by an adhesive.

Abstract: A method and apparatus for authenticating and authorizing a user of a device connected to a network. In one embodiment, a set of credential descriptors is generated that describes credentials that must be built for authenticating the user. The set of credential descriptors is provided to a first device, which includes a first master credential builder for building credentials corresponding to at least one of the credential descriptors. In the event that the first master credential builder does not build all of the credentials corresponding to the set of credential descriptors, another set of credential descriptors is provided to a second device, which includes a second master credential builder for building at least one credential remaining to be built. This process continues until all credentials have been built or a determination is made that they cannot be built.

Abstract: A method for reducing dynamic memory allocation includes designing a software program using a memory allocation module for allocating memory, analyzing the software program to determine a bound on dynamic memory allocation and modifying the program based on the analyzing. According to one aspect, the program is modified to use static memory allocation in lieu of dynamic memory allocation based on the analyzing. According to another aspect, the program is modified to reduce the amount of dynamically allocated memory based on the analyzing.

Abstract: A message gate is the message endpoint for a client or service in a distributed computing environment. A message gate may provide a secure message endpoint that sends and receives type-safe messages. A gate may have a gate name that is a unique ID that refers only to the gate. A gate may be implemented as a layer above a device's transport layer (e.g. networking sockets). The gate name for each gate may be bound to a transport reference. Multiple gates may share the same message transport. The transport reference may be a transport URI or socket reference and may provide a mechanism for naming an underlying transport and sharing the transport with other gates. Multiple local gates may include a reference to the same transport, however, each local gate may behave independently of the other local gates sending and receiving messages to and from its paired remote gate.

Abstract: The present invention is directed toward dynamic downloading of keyboard keycode data to a networked client. According to one or more embodiments of the present invention, a user logs into a networked client by presenting a smart card to a card reader attached to the client (or by some other authentication mechanism) and enters a PIN into the keyboard. The keycodes entered by the user logging into the client are obtained, translated into ASCII characters, and presented to the smart card. If the PIN is correct, the user is able to log in, otherwise the log in fails. In one embodiment, when the user enters the PIN, a translation table is downloaded from the server into the client. The client uses the translation table to convert the keycodes to ASCII text and presents the ASCII text to the smart card for authentication.

Abstract: A method for arithmetic overflow detection includes receiving a first instruction defined for a first processor having a first base, where the instruction comprises an operator and at least one operand having an operand type. The method also includes indicating whether the at least one operand has potential overflow based at least in part on the operator and the relationship between the operand type and a result type associated with the operator.

Abstract: A CORBA Gateway between CORBA-based applications and an enterprise manager may be configurable to manage various networked objects, such as printers, scanners, copiers, telephone systems, cell phones, phone systems, faxes, routers, switches, etc., which may be interconnected via networks. Various embodiments of the CORBA Gateway may include an Event Gateway which manages object events. The CORBA Event Gateway is designed to leverage existing Event Distribution Server (EDS) sinks to provide EDS filtering functionality and EDS object level access control functionality. The approach leverages existing EDS solutions by providing a common sink for all events/notifications and using a unique Event Port Registry to manage the subscriptions of various TMN clients that subscribe for such events/notifications. Generally, the approach described provides the capability to filter events according to criteria presented by client event subscriptions.

Abstract: A method of displaying an image of device test data includes receiving a first device test file and a second device test tile including a first plurality of bits and a second plurality of bits, respectively. The method may also include generating a first graphic image representative of the first device test file by depicting each of the first plurality of bits using a unique pixel of a display. The method may also include generating a second graphic image representative of the second device test file by depicting each of the second plurality of bits using a unique pixel of a display. Further, the method may include overlaying the second graphic image onto the first graphic image.

Abstract: A system for providing real-time cluster configuration data within a clustered computer network including a plurality of clusters, including a primary node in each cluster wherein the primary node includes a primary repository manager, a secondary node in each cluster wherein the secondary node includes a secondary repository manager, and wherein the secondary repository manager cooperates with the primary repository manager to maintain information at the secondary node consistent with information maintained at the primary node.

Abstract: One embodiment of a method of frame detection may involve storing data indicative of a pulse duration and a number of successive occurrences of pulses having that pulse duration for each of several different pulse durations detected within a first field of a composite synchronization signal. This process may be repeated for one or more other fields of the composite synchronization signal. The data stored for each of the fields may be compared, and a frame signal may be generated dependent on an outcome of said comparing.

Abstract: A processor including a large register file utilizes a dirty bit storage coupled to the register file and a dirty bit logic that controls resetting of the dirty bit storage. The dirty bit logic determines whether a register or group of registers in the register file has been written since the process was loaded or the context was last restored and, if written generates a value in the dirty bit storage that designates the written condition of the register or group of registers. When the context is next saved, the dirty bit logic saves a particular register or group of registers when the dirty bit storage indicates that a register or group of registers was written. If the register or group of registers was not written, the context is switched without saving the register or group of registers. The dirty bit storage is initialized when a process is loaded or the context changes.

Abstract: A cache pollution avoidance unit includes a dynamic memory dependency table for storing a dependency state condition between a first load instruction and a sequentially later second load instruction, which may depend on the completion of execution of the first load instruction for operand data. The cache pollution avoidance unit logically ANDs the dependency state condition stored in the dynamic memory dependency table with a cache memory “miss” state condition returned by the cache pollution avoidance unit for operand data produced by the first load instruction and required by the second load instruction. If the logical ANDing is true, memory access to the second load instruction is squashed and the execution of the second load instruction is re-scheduled.

Abstract: Methods for reducing the requirement for multiple test vector sub-set insertions of a test vector set on test equipment having a limited memory size. In one embodiment, a single, selective test vector sub-set is utilized in the pre-burn-in test phase of microprocessors and multiple test vector sub-set insertions of a test vector set are utilized in the post-burn-in test phase. In one embodiment, the single, selective test vector sub-set includes selected test vectors from some or all of the test vector sub-sets used in the post-burn-in test phase and is sized to fit within the fixed memory capacity of the test equipment. In another embodiment, a single, selective test vector sub-set is utilized in both the pre-burn and post-burn test phases.

Abstract: A computer-based method of interactively generating an index page displays a window including a list of index page types. Upon selection of one index page type in the list of index page types, a window including a list of index line types is displayed. Upon selection of one index line type in the list of index line types, a token string including a plurality of tokens is displayed. The plurality of tokens includes only tokens appropriate for the one index line. Upon selection of one token, or alternatively a window for entering content associated with the one token, user selectable attributes for the content associated with the at least one token are displayed.

Abstract: A method and apparatus for increasing the number of storage units. Specifically, the present invention describes a method for creating a plurality of virtual logical units (LUN) of storage from a plurality of existing volumes of storage for access by a plurality of host applications via a virtualization layer. The virtual LUNs are created by partitioning the existing volumes into a plurality of slices. Each of the plurality of slices is then mapped to the plurality of virtual LUNs. Furthermore, each of the plurality of virtual LUNs is masked to each of the plurality of host applications to provide access control. The plurality of host applications are transparently interfaced to the existing volume while preserving the original configuration of internal operating code or intelligence for interfacing with the plurality of existing volumes.

Abstract: Methods and apparatus for providing replacement functions for a set of system services include requesting a primitive function from one of the set of system services, the primitive function replicating the one of the set of system services with reduced functionality. A reference to the requested primitive function is then sent from the one of the set of system services.

Abstract: A method and computer program product for reducing colormap flashing on a display system where the display system has a single hardware colormap. The method includes the steps of intercepting a request from an application program for an allocation of a private colormap, and transparently simulating the allocation of the private colormap using the default colormap. In this manner, colormap flashing is reduced as the default colormap is used to satisfy private colormap requests.

Abstract: Techniques and modes of operation for using network interfaces in a single or multi-CPU environment are disclosed. The techniques provide a virtual “vertical perimeter” framework suitable for processing data through multiple network interfaces assigned to a single CPU. In this framework, techniques for installing and servicing a plurality of network interfaces with a single CPU utilizing virtual vertical perimeters and sub-queues is disclosed. A computer system including at least one CPU and a plurality of network interfaces configured to have more network interfaces than CPU's is disclosed. At least two of the interfaces are assigned to an associated CPU. The computer system includes an operating system with plurality of sub-queues and an associated sub-queue controller. The sub-queues are associated with at least two network interfaces assigned to the CPU.

Abstract: A system and method for controlling generation of and access to localized application values to applications. The system includes an administrative interface linked to a running application and to a communications network that is configured for receiving requests for application data from the application. The interface responds by determining obtaining localized application values from a cache or if not cached, from a central database or repository of network localized application values that is also linked to the communications network. Code or mechanisms are provided for creating and populating data structures or objects for storage in the cache. Mechanisms or background threads are also provided for monitoring changes to localized application values in the repository and automatically updating element values in the cache as and when they change.