Abstract: A multi-bank memory subsystem employing multiple memory modules. A memory subsystem includes a memory controller coupled to a memory bus. The memory bus includes a plurality of data paths each corresponding to a separate grouping of data lines. The memory bus is coupled to a first plurality of memory modules corresponding to a first memory bank. The first memory bank corresponding to a first range of addresses. The memory bus is also coupled to a second plurality of memory modules corresponding to a second memory bank. The second memory bank corresponding to a second range of addresses. A separate memory module of each of the first and the second memory banks is coupled to each data path of the memory bus. Memory modules that are coupled to the same data path are located adjacent to one another without any intervening memory modules coupled to other data paths.

Abstract: This invention provides for filtering instructions to obtain more precise event counts with a plurality of instructions having a counter enable bit, executing the instructions thereby causing a plurality of events, filtering the instructions, activating the counter enable bit if the instructions fall within the filter, which then determines whether an event counter coupled to the event is incremented.

Abstract: A fan carrier defines one or more enclosures with each enclosure receiving a fan unit. A first wall of the carrier includes at least one air vent that can be covered by a fire mesh. A second wall is substantially perpendicular to the first wall. The first and second walls form two walls of an enclosure for a fan unit. The second wall extends outwardly from the enclosure to define ears with locating lugs for locating the fan unit in a housing of the computer system. A fan subassembly includes the fan carrier and at least one fan secured therein, whereby the fan assembly can be installed in the computer system much more easily that a fan without the carrier. The fan subassembly can be located adjacent a vented portion of a housing wall of the computer system in a gap in a flange of that housing wall. The ear of the fan carrier is configured to overly a portion of that flange adjacent the gap and with the lug being received in a hole in said portion of the flange.

Abstract: An EMI-shielding riser card for reducing electromagnetic radiation from a computer enclosure is disclosed. The EMI-shielding riser card is a six-layer riser card having a connector adjacent its lower edge, such as a connector for an NLX system board. A cable connection socket is on the riser card a first distance away from the connector, and a plurality of traces in a signal layer of the riser card run between the cable connection socket and the connector. A first ground layer in the riser card is interposed between the signal layer and a first surface of the riser card. A second ground layer in the riser card is interposed between the signal layer and a second surface of the riser card. The first and second ground layers are configured to attach to a ground connection for a system board for which the riser card is adapted.

Abstract: A computer processor includes a number of register pairs LOCKADD/LOCKCOUNT to hold values identifying when a computer resource is locked. The LOCKCOUNT register is incremented or decremented in response to lock or unlock instructions, respectively. The lock is freed when a count associated with the LOCKCOUNT register is decremented to zero. In embodiments without LOCKOUT registers, the lock may be freed on any unlock instruction corresponding to the lock. In some embodiments, a computer object includes a header in which two header LSBs store: (1) a LOCK bit indicating whether the object is locked, and (2) a WANT bit indicating whether a thread is waiting to acquire a lock for the object.

Abstract: A method of optimizing speculative address load processing by a microprocessor includes identifying a speculative load, marking the speculative load, determining whether a miss occurs for the speculative load, and preventing use of the marked speculative load by the microprocessor if a miss occurs. A method of optimizing speculative address load processing by a microprocessor includes identifying a speculative load, marking the speculative load, inserting the marked speculative load into a load miss queue, determining whether a miss occurs for the speculative load, and preventing the load miss queue from committing the marked speculative load to cache if a miss occurs.

Abstract: A mechanism is disclosed for constructing dispatch tables which enable transitive method override. A dispatch table for a class C (wherein C is within a package P and is a subclass of superclass S) is constructed as follows. First, the S dispatch table is copied and is used as the starting point for the C dispatch table. Then, for each locally declared method m in C, the method m is checked to determine whether it has been marked public/protected. If so, then the S dispatch table is checked for a public/protected entry corresponding to a method having the same name as method m. If such an entry is found, then the corresponding entry in the C dispatch table is overridden. Otherwise, a new entry is allocated in the C dispatch table and is marked public/protected. In addition, the S dispatch table is checked for a package private (private to package P) entry corresponding to a method having the same name as method m.

Abstract: The resources of a partitioned cache memory are dynamically allocated between two or more processors on a multi-processor unit (MPU). In one embodiment, the MPU includes first and second processors, and the cache memory includes first and second partitions. A cache access circuit selectively transfers data between the cache memory partitions to maximize cache resources. In one mode, both processors are active and may simultaneously execute separate instruction threads. In this mode, the cache access circuit allocates the first cache memory partition as dedicated cache memory for the first processor, and allocates the second cache memory partition as dedicated cache memory for the second processor. In another mode, one processor is active, and the other processor is inactive. In this mode, the cache access circuit allocates both the first and second cache memory partitions as cache memory for the active processor.

Abstract: Improved techniques for allocating file descriptors are disclosed. According to one aspect, the file descriptors are stored in a tree-like data structure. The tree-like data structure is a data structure that includes a plurality of nodes arranged in the tree-like structure. The nodes have numeric values that are the file descriptors represented in a binary format. Each of the nodes also maintains an allocation count and an indication whether or not a particular node is available (i.e., unallocated). Preferably, the tree-like structure is an infix binary tree in which each node records the number of file descriptors within its right subtree (including itself) that are already allocated. The improved techniques allow file descriptors to be allocated much more efficiently than conventionally achieved.

Abstract: A method and apparatus for performing event-driven data transfer operations over a global computer network. Electronic Data Interchange (EDI) format data is extracted from a database stored on a first computer system connected to a global computer network. The transaction data extracted from the database is then monitored to determine whether the data is ready to be transmitted to a second computer system connected to the global computer network. When ready, the transaction data is transmitted to the second computer system. The second computer system, in turn, receives the transaction data, monitors the data to determine whether the data is ready to be merged into a database stored on the second computer system, and merges the data into the database. Embodiments of the invention allow for secure data transfer operations to be performed on-line and in real-time.

Abstract: A memory control unit has been developed. The control unit includes a command “spin wheel” which schedules the order of read and write commands to the memory. It also includes a read “spin wheel” which ensures proper timing of the read commands and a write “spin wheel” which ensures proper timing of the write commands.

Abstract: The invention is a method and apparatus for determining an approximate network distance using one or more reference points. In accordance with an embodiment of the invention, the method comprises the steps of selecting at least one reference point positioned along a path between first and second points of a network, generating first distance metric information associated with at least one path associating a first point and the at least one reference point, generating second distance metric information associated with at least one path associating a second point and the at least one reference point, and determining a total approximate distance between the first point and the second point along one or more paths based on the first and second distance metric information.

Abstract: A method for arithmetic overflow detection includes receiving a first instruction defined for a first processor having a first base, where the instruction comprises an operator and at least one operand having an operand type. The method also includes indicating whether the at least one operand has potential overflow based at least in part on the operator and the relationship between the operand type and a result type associated with the operator.

Abstract: A method for arithmetic expression optimization includes receiving an operator and at least one operand of a first instruction defined for a first processor having a first base. The method also includes converting the first instruction to a second instruction optimized for a second processor having a second base smaller than the first base when the at least one operand does not carry potential overflow beyond the second base or when the operator is insensitive to overflow. The method also includes converting instructions in an instruction chain to a wider base larger than the second base and smaller or equal to the first base when the at least one operand carries potential overflow beyond the second base and when the operator is sensitive to overflow. The chain is bounded by the second instruction and a third instruction that has been previously optimized and is the source of the potential overflow.

Abstract: A method for arithmetic expression optimization includes receiving an operator and at least one operand of a first instruction defined for a first processor having a first base. The method also includes converting the first instruction to a second instruction optimized for a second processor having a second base smaller than the first base when overflow is impossible based at least in part on the operator and the relationship between the operand type and the second base. The method also includes converting instructions in an instruction chain to a wider base larger than the second base and smaller or equal to the first base when the at least one operand carries potential overflow beyond the second base and when the operator is sensitive to overflow. The chain is bounded by the second instruction and a third instruction that has been previously optimized and is the source of the potential overflow.

Abstract: A method for arithmetic expression optimization comprises validating at least one input stack associated with a first instruction operable on at least one operand of a first type and optimizing the first instruction to a second instruction operable on at least one operand of a second type that is smaller than the first type based at least in part on the relative size of the first type and the second type. The method also comprises matching the second type with an operand type of at least one operand in the at least one input stack associated with the second instruction. The matching comprises changing the type of instructions in a chain of instructions to equal the second type if the operand type is less than the second type. The chain is bounded by the second instruction and a third instruction that is the source of the at least one operand.

Abstract: A computer system includes a processor capable of executing a plurality of N threads of instructions, N being an integer greater than one, with a set of global registers visible to each of the plurality of threads and a plurality of busy bit memory elements used to signal whether or not a register is in use by a thread. The processor includes logic to stall a read from global register if the thread reading the global register is a speculative thread and the busy bits for prior threads are set. The processor might also include a speculative load address memory, into which speculative loads from speculative threads are entered and logic to compare addresses for stores from nonspeculative threads with addressees in the speculative load address memory and invalidate speculative threads corresponding to the speculative load addresses stored in the speculative load address memory.

Abstract: An interconnect system connects two drawer management cards (DMCs) of a drawer. The drawer contains a plurality of independent nodes. The nodes are managed by at least two DMCs. Thus, if one of the DMCs fails, the other DMC can take over and manage the drawer. In one embodiment of the invention, the nodes within the drawer are managed through an Intelligent Platform Management Bus (IPMB). The other field replaceble units (FRUs) or hardware components in the drawer, such as fans, power supplies, etc., may be managed using an Inter Integrated Circuit bus (I2C). The first and second DMCs are interconnected with each other within a chassis of the drawer. The two DMCs are also interconnected with the management channels (e.g., buses) of the drawer. During power up, the first DMC and the second DMC on the drawer may determine, whether the DMC's are interconnected (or not). The DMCs then decide each of their roles (i.e., determining which DMC should be in an active state and which DMC should be in a standby state).

Abstract: A cache memory includes a plurality of memory chips, or other separately addressable memory sections, which are configured to collectively store a plurality of cache lines. Each cache line includes data and an associated cache tag. The cache tag may include an address tag which identifies the line as well as state information indicating the coherency state for the line. Each cache line is stored across the memory chips in a row formed by corresponding entries (i.e., entries accessed using the same index address). The plurality of cache lines is grouped into separate subsets based on index addresses, thereby forming several separate classes of cache lines. The cache tags associated with cache lines of different classes are stored in different memory chips. During operation, the cache controller may receive multiple snoop requests corresponding to, for example, transactions initiated by various processors.

Abstract: A method for arithmetic expression optimization includes receiving a first instruction defined for a first processor having a first base, the first instruction including an operator and at least one operand, converting the first instruction to a second instruction optimized for a second processor having a second base when all operands do not carry potential overflow or when the operator is insensitive to overflow, the second base being smaller than the first base, and converting to a wider base a third instruction that is the source of the overflow when the at least one operand the potential for overflow and when the operator is sensitive to overflow.