Abstract: Clocked half-rail differential logic circuits with sense amplifier and shut-off are activated by a delayed clock and include a sense amplifier circuit that is triggered by a second delayed clock and a shut-off device. The addition of the sense amplifier circuit, and second delayed clock signal allows the sense amplifier circuit to act as the driver and therefore there is no need for increasing the size of the differential logic network to provide a driver function. The addition of the shut-off device provides a half-rail differential logic circuit with shut-off that does not experience the large or “dip” experienced by prior art half-rail differential logic circuits and is therefore more power efficient.

Abstract: A dual port memory cell is provided. The dual port memory cell includes a storage cell. A first bitline pair defining access to the storage cell by a first port and a second bitline pair defining access to the storage cell by a second port are defined. Each bitline of the first and second bitline pairs is defined from metallization line features, and the first bitline pair is defined on one side of the storage cell and the second bitline pair is defined on the other side of the storage cell. The bitlines of the first port are physically separate from the bitlines of the second port.

Abstract: A control board controls operation of a plurality of ventilation fans and generates a fault signal upon occurrence of a predetermined fault condition. The control board includes a control circuit in a circuit board, an interface connector connected to the control circuit and mounted to the circuit board, and control connectors connected to the circuit and mounted to the circuit board. The control connectors are configured to connect the control circuit to ventilation fans or other components to be controlled. The control connectors are connected to a fault detection device of the control circuit operable to generate a fault signal upon occurrence of a predetermined fault condition at the control connectors.

Abstract: An external cache management unit for use with a 3D-RAM frame buffer and suitable for use in a computer graphics system is described. The unit may reduce power consumption within the 3D-RAM by performing partial block write-back according to status information stored in an array of dirty tag bits. Periodic level one cache block cleansing is provided for during empty memory cycles.

Abstract: A synchronous dynamic random access memory controller has a high speed interface and a low speed interface. The high speed interface has a buffer with entries for receiving transactions, and the buffer has a valid bit for each entry. The entries store transactions that are received from a high speed bus. The low speed interface retrieves transactions from the buffer. The high speed interface and low speed interface each have state machines that synchronize the high speed and low speed interfaces using the valid bit for each of the entries.

Abstract: A system by which resource adapters may be utilized in client server computer configurations utilizing enterprise information systems is disclosed. A connector provider develops a set of Java interfaces and classes as part of its implementation of a resource adapter. These Java classes implement connector architecture specified contracts and implement EIS specific functionality provided by the resource adapter. The development of a resource adapter can also require use of native libraries that are specific to the underlying EIS. The Java interfaces and classes and native libraries, help files, documentation and other resources (as necessary) are then packaged together with a deployment descriptor to create a resource adapter module. The resource adapter module defines the contract between a connector provider and deployer for the deployment of a resource adapter in the client server environment.

Abstract: A method for preferentially shielding a signal to increase implicit decoupling capacitance is provided. The signal is preferentially shielded by using a probability of the signal being at a specific value to assign a shield potential. Further, an integrated circuit that preferentially shields a signal to increase decoupling capacitance by using a probability of the signal being at a specific value to assign a shield potential is provided. Further, a computer system for preferentially shielding a signal to increase decoupling capacitance by using a probability of the signal being at a specific value to assign a shield potential is provided. Further, a computer readable medium having executable instructions for preferentially shielding a signal to increase implicit decoupling capacitance by using a probability of the signal being at a specific value to assign a shield potential is provided. Further, a method to increase system performance by increasing implicit decoupling capacitance is provided.

Abstract: One embodiment of the present invention provides a system that facilitates speculative load operations in a multiprocessor system. The system operates by maintaining a record of speculative load operations that have completed at a processor in the multiprocessor system, wherein a speculative load operation is a load operation that is speculatively initiated before a preceding load operation has returned. Next, the system receives an invalidation signal at an L1 cache that is coupled to the processor, wherein the invalidation signal indicates that a specific line in the L1 cache is to be invalidated. In response to this invalidation signal, the system examines the record of speculative load operations to determine if there exists a matching speculative load operation that is completed and is directed to the same location in the L1 cache that the invalidation signal is directed to.

Abstract: A memory module having balanced data input/output contacts. A memory module includes a printed circuit board having an edge connector and a plurality of memory integrated circuits. The edge connector may be adapted for insertion into a socket of a motherboard of a computer system, for example. The edge connector includes a plurality of contact pads on both sides of the printed circuit board. The contact pads are configured to convey data signals, power and ground to and from the printed circuit board. The power and ground contact pads alternate along the edge connector. There are no more than four data signal contact pads without intervening power or ground contact pads.

Abstract: A method and apparatus of performing active update notification. Components of an application are able to specify interest in a data object or set of data objects by registering an interest object with an update management component of the application. The interest object specifies the interested application component, as well as the identity of one or more data objects or an attribute value or range of values to associate with data objects. When modifications are made to data objects corresponding to the registered interest objects, the interested application component or components receive an update notification from the update management component. In one embodiment, active update notification is performed within a multi-tier application. An update management component exists at the application server on the application tier, as well as at each client in the client tier.

Abstract: The present invention provides a method and apparatus for updating a directory cache. The method comprises detecting a memory access transaction, determining a retention value based on the type of memory access transaction, and storing the retention value in an entry associated with the memory access transaction.

Abstract: A dual edge-triggered flip-flop that may be programmably reset independent of a clock signal is provided. Using an externally generated reset value, the dual edge-triggered flip-flop may be asynchronously programmed to reset to either a logical high or a logical low. Further, a dual edge-triggered flip-flop that may be set to multiple triggering modes is provided. Using an externally generated enable signal, the dual edge-triggered flip-flop may be set to function as a single edge-triggered or a dual edge-triggered device. Thus, the dual edge-triggered flip-flop may be used multiple types of computing environments.

Abstract: Several embodiments of a computer system are described which achieve separation of control and data paths during data transfer operations, thus allowing independent scalability of storage system performance factors (e.g., storage system iops and data transfer rate). In one embodiment, the computer system includes a data switch coupled between a host computer and one or more storage devices. A storage controller for managing the storage of data within the one or more storage devices is coupled to the switch. The switch includes a memory for storing data routing information generated by the controller, and uses the data routing information to route data directly between the host computer and the one or more storage devices such that the data does not pass through the storage controller. Within the computer system, information may be conveyed between the host computer, the switch, the one or more storage devices, and the storage controller according to a two party protocol such as the Fibre Channel protocol.

Abstract: The present invention provides a method for performing an inversion and multiply in a single operation as a polynomial divide operation. As a result, the invention reduces the number of mathematical operations needed to perform point doubling and point addition operations. An elliptic curve cryptosystem using the present invention can be made to operate more efficiently using the present invention. An elliptic curve crypto-accelerator can be implemented using the present invention to dramatically enhance the performance of the elliptic curve cryptosystem. The invention uses five registers A, B, U, V, and M, to accomplish a polynomial divide operation. Four registers A, B, U, and V are initialized with values so that the registers maintain a number of invariant relationships. The registers store initial values a(t)=x(t), u(t)=y(t), b(t)=prime(t), and v(t)=0. Here the polynomials in registers A, U, B, and V are denoted as a(t), u(t), b(t), and v(t), respectively.

Abstract: A system for managing storage accesses for rate guaranteed continuous multimedia data streams and non-rate-guaranteed storage requests may include a plurality of rate guaranteed requestors for multimedia streams and one or more non-rate guaranteed requesters. A disk scheduler may also be included. The disk scheduler may have a guaranteed rate queue for queuing storage requests from the rate guaranteed requestors and a non-rate-guaranteed queue for queuing requests from the non-rate-guaranteed requestors. The disk scheduler may also include a bandwidth allocator coupled to the guaranteed rate queue and the non-rate-guaranteed queue and further coupled to a storage system. The bandwidth allocator may be configured to allocate bandwidth of the storage system between the guaranteed rate queue and the non-rate-guaranteed queue according to a predetermined ratio.

Abstract: A mechanism for merging multiple source policies to derive a resultant policy is disclosed. The source policies, which may represent sets of laws/regulations, and which may comprise zero or more entries with each entry comprising an identifier and a set of one or more limitations, are merged by first selecting a current entry in a first source policy. Then a determination is made as to whether there is an entry in a second source policy which corresponds to the current entry. If so, then the limitations in the current entry are processed with the limitations in the corresponding entry to derive a set of resultant limitations. The limitations are processed such that the resultant limitations comprise the most restrictive limitations of the current entry and the corresponding entry. By doing so, it is ensured that the resultant limitations comply with both the first and the second source policies.

Abstract: One embodiment of the present invention provides a system that marks memory elements based upon how information retrieved from the memory elements affects speculative program execution. This system operates by allowing a programmer to examine source code that is to be compiled into executable code for a head thread that executes program instructions, and for a speculative thread that executes program instructions in advance of the head thread. During read operations to memory elements by the speculative thread, this executable code generally causes the speculative thread to update status information associated with the memory elements to indicate that the memory elements have been read by the speculative thread. Next, the system allows the programmer to identify a given read operation directed to a given memory element, wherein a given value retrieved from the given memory element during the given read operation does not affect subsequent execution of the speculative thread.

Abstract: Coupling capacitance is used to balance skew in a network. In one embodiment, the coupling capacitance exerted by shielding wires oppositely adjacent one or more signal wires in a network is utilized to vary the speed of a signal carried on the one or more signal wires to balance skew in the network.

Abstract: A field and/or customer replaceable packaged refrigeration module with thermosyphon is suitable for use in standard electronic component environments. The field replaceable packaged refrigeration module portion is self-contained and is specifically designed to have physical dimensions similar to those of a standard air-based cooling system, such as a fined heat sink or heat pipe. The field replaceable packaged refrigeration module is coupled to a thermosyphon and serves to lower the base temperature of the thermosyphon sub-system, thereby allowing intermittent operation of the field replaceable packaged refrigeration module with the thermosyphon sub-system.

Abstract: The present application describes an apparatus and method for dispensing interface materials for electronic packages. According to some embodiments, a cooling radiator is attached using adhesive interface material (e.g., on the perimeter, edges, distributed spots or the like) to an electronic package. After the adhesive interface material cures, the thermal interface material is dispensed (e.g., thorough an opening in the cooling radiator, adhesive interface material or the like). The dispensing of the thermal interface material does not leave a gap between the adhesive interface material and thermal interface material thus providing a better thermal performance and hence, enhanced power dissipation for the electronic package.