Abstract: Methods and apparatus for creating compressed versions of regular objects are disclosed. According to one aspect of the present invention, a method for creating a compressed version of an object that stores a first representation of a set of data on a heap structure of an object-based computing system includes determining when the first representation of the set of data is suitable for compression. If the first representation of the set of data is compressible, it is compressed to form a second representation of the set of data, and a second portion of memory is allocated on the heap structure. The second portion of memory is substantially smaller than a first portion of memory occupied by the object. Finally, the method includes writing the second representation of the set of data into the allocated second portion of memory. In one embodiment, the method includes resetting a pointer that identifies the object to identify the allocated second portion of memory, and removing the object from the heap structure.

Abstract: The analysis of the lifetime of objects in a garbage-collected system may be accomplished quickly and effectively using reference counts and cyclic garbage analysis. A reference count is maintained for each of the objects to indicate the number of incoming pointers. Each time the graph structure is altered, the reference counts are updated. Timestamps are recorded each time the reference count for objects change. If a reference count goes to zero, the corresponding object may be indicated as dead. A garbage collection need only be run once (perhaps at the end), and after it is run the system may indicate which objects are cyclic garbage. The timestamps for objects which are cyclic garbage are then reviewed in reverse chronological order. For each timestamp found, the corresponding object and any object reachable from the corresponding object are indicated as dead. These objects are then removed from the set of cyclic garbage.

Abstract: A method for controlling operation of a bus and components coupled thereto is provided. The method is comprised of receiving a request for a bus transaction from one of the components coupled to the bus. Thereafter, the frequency of a clock signal supplied to at least the requesting component is increased, and the requested bus transaction is serviced. The frequency of the clock signal supplied to at least the requesting component is decreased upon completion of the requested bus transaction.

Abstract: Several methods are presented for achieving a desired value of electrical impedance between parallel planar conductors of an electrical power distribution structure by electrically coupling multiple bypass capacitors between the planar conductors. The methods include bypass capacitor selection criteria based upon simulation results. An exemplary electrical power distribution structure produced by one of the methods includes a pair of parallel planar conductors separated by a dielectric layer, and n discrete electrical capacitors electrically coupled between the planar conductors, where n≧2. The n capacitors have substantially the same capacitance C, mounted resistance Rm, and mounted inductance Lm. The electrical power distribution structure achieves an electrical impedance Z at a mounted resonant frequency fm-res of the capacitors. The mounted resistance Rm of each of the n capacitors is substantially equal to (n·Z). The mounted inductance Lm of each of the n capacitors is less than or equal to (0.

Abstract: A two-dimensional image contains a number of objects, which are represented in layers from front to rear, perpendicularly with respect to the two-dimensional image plane. Each object is defined by a polygon, which encloses a distinguishably represented area of the two-dimensional image. A method orders polygons in a plurality of polygons of a two-dimensional image in a sequence defined by layering of the polygons in the two-dimensional image. A first polygon in the sequence is a reference polygon. The method sequentially assigns each polygon in the sequence, starting with the reference polygon, to one of a plurality of layers so that within a given layer no polygon assigned to the given layer (i) overlaps with another polygon in the given layer, and (ii) is included within another polygon in the given layer.

Abstract: A systematic methodology to analyze a full scan dump is presented. The methodology is knowledge-based, i.e., the methodology intelligently processes a full scan dump using knowledge of the system from which the full scan is obtained.

Abstract: A method and system for leasing storage locations in a distributed processing system is provided. Consistent with this method and system, a client requests access to storage locations for a period of time (lease period) from a server, such as the file system manager. Responsive to this request, the server invokes a lease period algorithm, which considers various factors to determine a lease period during which time the client may access the storage locations. After a lease is granted, the server sends an object to the client that advises the client of the lease period and that provides the client with behavior to modify the lease, like canceling the lease or renewing the lease. The server supports concurrent leases, exact leases, and leases for various types of access. After all leases to a storage location expire, the server reclaims the storage location.

Abstract: Apparatus and method are disclosed for thermally managing a display. A display may be tiltably coupled to a base, and the display may have a tilt sensor disposed therein for providing a tilt output when the display is tilted beyond a tilt threshold. Further aspects include a temperature sensors disposed for providing a high- or low-temperature threshold output when the display the exceeds predetermined temperature thresholds. The disclosure provides for producing a warning signal to the user when sensed signals are positive, and for producing a sleep signal to protect the display from thermal damage.

Abstract: A delay locked loop design uses a diode operatively connected to a loop filter capacitor to control a leakage current of the loop filter capacitor. By positioning a diode in series with the loop filter capacitor, a voltage potential across the loop filter capacitor is reduced, thereby reducing the leakage current of the loop filter capacitor. Moreover, the leakage current of the loop filter capacitor is controlled in that it cannot exceed the current through the diode. Control and reduction of the loop filter capacitor leakage current leads to more reliable and stable delay locked loop behavior.

Abstract: Novel methods and apparatus to enhance thermal performance of IC packages are disclosed. In an embodiment, a method of enhancing thermal uniformity across a semiconductor device is disclosed. The method includes providing the semiconductor device. The semiconductor device has a plurality of thermal regions. A first thermal region of the plurality of thermal regions has a different temperature than a second thermal region of the plurality of thermal regions. The method further provides a thermal enhancement material substantially adjacent to the first and second thermal regions. In another embodiment, a thermal conductivity of the thermal enhancement material is adjusted in relation to a temperature effecting the thermal enhancement material.

Abstract: A system is presented that selectively enables expression folding during compilation of a program, wherein the compilation converts the program from source code into executable code. The system operates by forming an expression tree for an expression within the source code which includes an assignment operator. If the assignment operator is a first assignment operator that is a value assignment, only the computed value can be used in subsequent expressions, thereby disabling expression folding during the compilation process. On the other hand, if the assignment operator is a second assignment operator that specifies an expression assignment, the entire expression can be used in place of the variable on the left of the expression assignment, thereby enabling expression folding during the compilation process. The expression can include a mathematical interval. The expression folding can involve substituting a first expression for a variable within a second expression, and then simplifying the result.

Abstract: A method and mechanism operating within the Application layer of the architectural model for maintaining high availability in a two node computer network. A backup connection is created wherein a second network card is added to each node of a two node network and a crossover cable is coupled between them. Each backup network card is configured with dummy parameters and taken down upon startup. A failover mechanism operating within the Application layer monitors the original, primary network connection. Upon detecting a failure of the primary connection, the failover mechanism halts monitoring of the primary connection, configures the backup network interface with the parameters of the primary network interface, and brings up the backup interface.

Abstract: A method for achieving a desired value of electrical impedance between conductors of an electrical power distribution structure by electrically coupling multiple bypass capacitors and corresponding electrical resistance elements in series between the conductors. The resistance elements may be annular resistors, and may provide the designer a greater degree of control of the system ESR. The annular resistors may comprise a first terminal, an annular resistor, and a second terminal. The second terminal may be located within the confines of the annular resistor. The annular resistors may be printed onto a conductive plane (e.g. a power plane or a ground plane), or may be a discrete component.

Abstract: A method includes interfacing with a field replaceable unit (FRU) having a memory device configured to store a FRUID image including at least status data. The status data is extracted from the memory device. Repair information associated with a repair of the field replaceable unit is received. The repair information is stored in the memory device. A system includes a field replaceable unit (FRU) and a FRU tool. The FRU includes a memory device configured to store a FRUID image including at least status data. The FRU tool is configured to interface with the FRU, extract the status data from the memory device, receive repair information associated with a repair of the field replaceable unit, and store the repair information in the memory device.

Abstract: A method of automatically performing a component test at any number of locations in a distributed environment is disclosed. In general, in order to assure compatibility of the various components in an enterprise computing system, a service test is created as part of a compatibility test suite and passed to a test application server having a test application program. The test application program includes a generic vehicle class that includes a plurality of vehicle class invokers each of which is used to implement each of the object types that are run in each of a plurality of containers. During the build process of the CTS, each service test is automatically packaged with each of the appropriate vehicle classes so that each can be deployed into and run within the associated container.

Abstract: Methods for reducing the requirement for multiple test vector sub-set insertions of a test vector set on test equipment having a limited memory size. In one embodiment, a single, selective test vector sub-set is utilized in the pre-burn-in test phase of microprocessors and multiple test vector sub-set insertions of a test vector set are utilized in the post-burn-in test phase. In one embodiment, the single, selective test vector sub-set includes selected test vectors from some or all of the test vector sub-sets used in the post-burn-in test phase and is sized to fit within the fixed memory capacity of the test equipment. In another embodiment, a single, selective test vector sub-set is utilized in both the pre-burn and post-burn test phases.

Abstract: Predetermined and standardized path templates are introduced between points and/or elements in an integrated circuit layout. According to one embodiment of the invention, the standardized path templates are made up of two or more parallel tracks of path segments, with or without corresponding perpendicular path segments. According to the invention, the path segments are connected as needed to form serpentine or non-serpentine paths of the required length.

Abstract: A method for rapidly mapping a bitmask returned by a Single Instruction Multiple Data (SIMD) computer compare instruction is provided. A user supplied partitioned mapping variable includes multiple mapping elements. Each of the multiple mapping elements is applied to the inputs of a different one of multiple digital multiplexers. The bitmask returned by the SIMD compare instruction is applied to the selects or all of the multiple digital multiplexers. Each multiplexer outputs one bit, as selected by the bitmask, from the respective mapping element applied to each multiplexer. The one bit outputs are accumulated in a mapped output variable as a mapped bitmask.

Abstract: In some embodiments, the present application describes an on-chip system and method of determining the effective locked frequency of a PLL. The locked frequency of the PLL is used to latch a test signal through various latching devices (flip-flops or the like). Various different delays are selectively applied to the test signal to provide a delayed test signal and the delayed test signal is measured to determined whether the delay in the test signal matches the jitter in the locked frequency of the PLL. When the delay in the test signal match the jitter in the locked frequency of the PLL, the respective delay of the test signal is used to determine the effective locked frequency of the PLL.

Abstract: An arithmetic logic unit (ALU) implemented with complementary pass gate logic using propagate, generate, and kill is provided. Broadly speaking, the ALU is a 64-bit ALU using a multi-stage global carry chain to generate intermediate fourth-bit carries that are folded with local four-bit sums to efficiently generate a final sum output. The ALU implements ones complement subtraction by incorporating a subtraction select signal to invert each bit of a second operand. The ALU circuitry implements a push-pull methodology to improve performance.