Abstract: The present invention provides a method and apparatus for hybrid checkpointing which captures the entire address space of a process: both language internal and language external (native) memory and program state. Initially, the invention halts a currently active process. Next, the invention gets and records the native state of a process, including threads. Next, the invention gets and records the internal state of a process and utilizes persistent object caching. Thereafter, the invention checkpoints the process. In one embodiment, the invention builds and utilizes a catalogue. The catalogue records the native and internal states from prior checkpoints. Upon the invocation of a new checkpoint, the invention accesses the catalogue and determines what native and internal states have changed since the last checkpoint. If some of the states have changed the invention updates the catalogue and only checkpoints those changed states, thereby operating more efficiently.

Abstract: A method for load balancing including creating a network, having a plurality of servers, to service a single multicast address using a source specific join, where the source specific join allows each of the plurality of servers to specify a source internet protocol address range that each of the plurality of servers services. Further, method includes reallocating the source internet protocol address range specified for at least one of the plurality of servers using a load balancing policy and a control multicast channel while at least one of the plurality of servers is handling communications.

Abstract: A system that allows a programmer to specify a set of constraints that the programmer has adhered to in writing code so that a compiler is able to assume the set of constraints in disambiguating memory references within the code. The system operates by receiving an identifier for a set of constraints on memory references that the programmer has adhered to in writing the code. The system uses the identifier to select a disambiguation technique from a set of disambiguation techniques. Note that each disambiguation technique is associated with a different set of constraints on memory references. The system uses the selected disambiguation technique to identify memory references within the code that can alias with each other.

Abstract: In a Pure Fill Via Area (PFVA) extraction design flow, the extracted PFVAs may violate the minimum via spacing rule with the existing vias and may also violate the minimum via spacing rule among themselves. Such extracted PFVA violations may be corrected in an automatable design flow not requiring user intervention by removing any portion of a PFVA falling within a minimum via spacing rule of an existing via, to form a DRC-clean PFVA relative to existing vias, and removing any portion of a DRC-clean PFVA falling within the minimum via spacing rule of another DRC-clean PFVA.

Abstract: A method for allocating decoupling capacitor cells in an integrated circuit (IC) design, includes (a) obtaining geometrical information of rectangular areas in the IC design, each of the rectangular areas not intersecting any design figure in selected metal layers of the IC design in a design area, (b) determining possible locations for rows of decoupling capacitor cell arrays to be placed in the rectangular areas, a row including a set of cell arrays to be placed across the rectangular areas in a direction of a first coordinate axis of the design area, (c) determining for each possible location a number of decoupling capacitor cells included in the row, and (d) selecting row locations satisfying a certain design rule from among the possible locations in a descending order of the number of the decoupling capacitor cells.

Abstract: In a multi-wide object class design layout, an automatic extraction of pure fill via areas (PFVA) among multi wide class objects treats the virtual boundaries of the wide objects differently than non-virtual boundaries to allow an extracted pure fill via area to extend across a virtual edge of a wide class object. An exemplary method is provided for deriving one or more pure fill via areas for geometries on a first layer in a design layout having multi-wide object classes on the first layer. The exemplary method includes forming a Current PFVA, initially as a PFVA for the geometries of the layer, and successively adjusting the Current PFVA for each higher wide object class corresponding to the geometries, to accommodate the respective enclosure rules for each higher wide object class.

Abstract: A redundant via design rule check is preferably performed on multi-wide object class design layouts to ensure that each connection area between two conductive layers has at least a certain number of vias and/or has vias placed appropriately to reduce the risk of via failure due to vacancy concentration of isolated vias. In exemplary embodiments, a redundant via design rule check preferably ensures that for vias placed within a connection area of a metal feature (or within a localized region of a larger metal geometry) that is both greater than a certain width and greater than a certain area in size, the vias are both sufficient in number and/or suitable in their location. Vias located inside a geometry but falling outside a virtual edge of a wide class object may be included to satisfy exemplary rules.

Abstract: A method and apparatus for digital content access control comprises sending a digital content request comprising a request for digital content to a content provisioner capable of authenticating the request, receiving an authenticated digital content request in response to the digital content request and sending the authenticated digital content request to a content repository that provides storage for the digital content.

Abstract: In a multi-wide class design layout, design rule checks for enclosure of multi wide class objects prevent false errors or false passes by performing such checks against the non-virtual boundaries of a wide class object, and not against the virtual boundaries. An exemplary embodiment provides a method for identifying as a violation, for each wide class wi object, any geometry on another layer which is located at least partially inside the wi object and has any portion thereof located within a distance encli of any non-virtual boundary of the wi object. The exemplary method is preferably performed using effective wide class objects.

Abstract: A system for managing cables is disclosed herein. A preferred aspect of the system comprises a flat panel monitor having a front surface, a rear surface, a left side surface and a right side surface. The system also comprises a plurality of downwardly facing cable portals coupled to the rear surface of the flat panel monitor and a stand coupled to the rear surface of the flat panel monitor, wherein the flat panel monitor is forwardly rotatable on a horizontal axis; and a plurality of releasably connectable retaining member are coupled to the rear surface of the flat panel monitor.

Abstract: A system is described for rearranging data units of a data word in accordance with a mask word, the mask word having a plurality of mask bits each associated with a data unit, each mask bit having one of a set condition or a clear condition. The system includes a control module and a shifter module. The control module is configured to generate, for each mask bit, values identifying the number of mask bits to the left of the respective mask bit which have one of the set condition or the clear condition and the number of mask bits to the right of the respective mask bit which have the other of the set condition or the clear condition. The shifter module is configured to shift data units of the data word in accordance with the values generated by the control module.

Abstract: A memory module comprising a printed circuit board having mounting locations for a plurality of memory chips. A line driver having a plurality of outputs for each input is used to drive address and control signals to the chips, with each set of outputs coupled to a subset of the chips. Memory access time is improved by limiting subset size and thereby limiting driver loading. Subsets may correlate to banks of memory chips. Access time is substantially the same for a module with a plurality of banks of memory chips as it is for a module with only one bank of chips. Computer memory may be efficiently exchanged by using only such memory modules, allowing higher clock speed since the range of memory access times is reduced and requiring no change to system memory configuration or settings. Memory modules having differing capacities can be easily interchanged in the system.

Abstract: An integrated TDR for locating transmission line faults. An integrated circuit comprises a transmitter, a path coupled to the transmitter, and a TDR receiver integrated with the transmitter for analyzing a reflected signal from the path. The TDR receiver compares the reflected signal with a variable reference signal to generate a logic state at a sampling instant determined by a timebase generated by a sampling circuit. The reflected signal equals the variable reference signal when the logic state transitions. The reference signal and the corresponding timebase value are recorded at the logic state transition. A waveform is generated from the recorded reference signal and its corresponding timebase value. A reference point for the waveform is determined. The location of a fault on the transmission line can be determined from the timebase value difference between the reference point and the fault.

Abstract: An apparatus to overcome a metastable state in a communication system employing a common clock period includes a first latch and a second latch, the first latch being clocked by a clock signal and the second latch being clocked by an inverted version of said clock signal, each of the first and second latches receiving a data stream. A delay device delays the output of the second latch by one half of a cycle of the clock signal. A multiplexer outputs the output of the first latch when the received data stream does not exhibit metastability relative to the clock signal and outputs the output of the delay device in the presence of metastability. By latching the data according to the inverted clock, the data is not latched during state transitions thereof and metastability is avoided. The delay device re-synchronizes the latched data with the active edges of the clock signal.

Abstract: Methods and apparatus for performing fast subtype checks during program execution are disclosed. According to one aspect of the present invention, a method for determining whether a class associated with an object that is a part of an object-based computing system is a subtype of another type includes obtaining a candidate type from a dynamic storage location that is associated with a class which is associated with the object, and comparing the candidate type against a first type that is potentially the same as the candidate type. A determination is then made as to whether the candidate type is substantially equal to the first type. When the determination is that the candidate type is substantially equal to the first type, an indication that the candidate type is a subtype of the first type is provided. In one embodiment, the candidate type obtained from the dynamic storage location is obtained from a cache element in the class associated with the object.

Abstract: One embodiment of the present invention provides a system that facilitates generating a simulation module for testing a system design. The system operates by receiving a system specification, which specifies correct behavior for modules within the system design. The system also receives modules that are individually designed to this system specification. The system then compares the modules with the system specification to identify nonfunctioning modules that can include either missing modules or incorrect modules. The system also determines an interface for the nonfunctioning modules from the system specification, which specifies input and output requirements for these nonfunctioning modules. The system then generates the simulation module. This simulation module can function in place of the nonfunctioning module and can simulate a functionality assigned to the nonfunctioning module.

Abstract: An improved high-speed domino logic circuit uses two delayed clock signals, CLKD and CLKDBAR, and three transistors to introduce a transition delay time. According to the invention, the delayed clock signals are used in conjunction with the three added transistors to avoid the contest or “fight” between a first node and the keeper transistor in the event of a path to ground being created through the logic block portion of improved high-speed domino logic circuit. The improved high-speed domino logic circuits of the invention, in contrast to prior art domino logic circuits, can be designed to have high noise immunity and increased speed. In addition, since according to the invention, only three new transistors are required, the modification of the invention is space efficient and readily incorporated into existing designs.

Abstract: A blockage aware zero skew clock routing method for calculating the distance, and therefore the delay, between two points takes into account any blockages along the path between the two points and therefore creates a more usable and realistic measure of delay and allows for minimization, or elimination, of clock skew in the system being designed using the method of the invention.

Abstract: The present application describes a method and an apparatus for facilitating increased uniformity and diffusion of force transfer on a bare die electronic package for example, when such electronic package is attached to a circuit board. Additional force absorbent material is applied around a bare die in the bare die electronic package. The force applied to the bare die electronic package can be distributed to the additional force absorbent material. A curable force absorbent material is dispensed around the bare die in the bare die electronic package. The surface of the curable material is substantially parallel with the surface of bare die thus facilitating a substantially uniform force distribution through the bare die and curable material resulting in a robust bare die electronic package.