Abstract: Clocked full-rail differential logic circuits with sense amplifier and shut-off are activated by a delayed clock and include a sense amplifier circuit that is triggered by a second delayed clock and a shut-off device. The addition of the sense amplifier circuit, and second delayed clock signal allows the sense amplifier circuit to act as the driver and therefore there is no need for increasing the size of the differential logic network to provide a driver function. The addition of the shut-off device provides a full-rail differential logic circuit with shut-off that does not experience the large “dip” experienced by prior art full-rail differential logic circuits and is therefore more power efficient.

Abstract: A method for comparing two delimited strings, each of which has a plurality of substrings, includes pairing each substring in one of the delimited string with a corresponding substring in the other one of the delimited strings. The method further includes computing a proximity value for each pair of substrings, and computing a set of decaying weights corresponding to the pairs of substrings, multiplying the proximity value for each pair of substrings by the corresponding weight, and summing the weighted proximity values to obtain a strength of match between the delimited strings.

Abstract: A power sub-system controls a supply of power to a field replaceable unit for electronic equipment. The power sub-system includes a power controller that is arranged, in response to the detection of a fault, to switch off the supply of power to a field replaceable unit. The power controller is then responsive to a sequence of two events to switch on the supply of power to the field replaceable unit. The first event is a first change in state of an interlock signal indicative of the field replaceable unit being released. The second event is a change of state of the interlock signal indicative of a field replaceable unit being secured in position. Automatic power management can thus provided with requiring a maintenance engineer to restore power manually, this being achievable simply by the removal and replacement of the field replaceable unit. The field replaceable unit includes an interlock mechanism for locking the field replaceable unit in the electronic equipment.

Abstract: One embodiment of the present invention provides a system that considers inductive effects while analyzing noise and propagation delay effect in a circuit layout. The system operates by first receiving the circuit layout, wherein the circuit layout specifies a plurality of nets that carry signals between circuit elements. Next, the system converts a given net into a single signal path, which is divided into a number of segments. The system then calculates inductance, capacitance, and resistance values for each segment. Next, the system uses these inductance, capacitance, and resistance values to produce a model for each segment. The system then couples together models for each segment into a model for the given net. The system uses the model for the given net to determine a noise and propagation delay effect through the given net.

Abstract: A communications arrangement is described for facilitating transfer of messages among a plurality of processes in a computer system. The communications arrangement comprises a channel data structure, a status daemon and an exit handler. The channel data structure includes a channel status flag normally having one of a plurality of conditions, and a plurality of storage locations each configured to receive message information. The status daemon is configured to determine the operational status of the processes. The exit handler is configured to, in response to the status daemon determining a predetermined condition in connection with at least one of the processes, condition the channel status flag to another of the conditions, thereby to indicate to the other processes a failure condition in connection with the communications arrangement.

Abstract: The present invention uses feedback to determine the size of an object cache. The size of the cache, (i.e., its budget), varies and is determined based on feedback from the persistent object system. Persistent objects are evicted from the cache if the storage for persistent objects exceeds the budget. If the storage is less than the budget then persistent objects in the heap are retained while new persistent objects are added to the cache.

Abstract: A system is disclosed for providing, from an input data word comprising a plurality of input data units having an input arrangement and a mask word comprising a plurality of mask bits each associated with one of the data units, an output data word in which the data units are arranged according to the mask bits. The system includes a bit balancer module and a plurality of rearrangement modules. The bit balancer module is configured to divide the input data units comprising the input data word into a plurality of data word portions, each data unit being assigned to one of the data word portions based on a pattern of mask bits of the mask word relative to the mask bit associated with the respective data unit. Each rearrangement module is configured to provide, from one of the data word portions and associated mask bits, an output data word portion in which the data units are arranged according to the mask bits.

Abstract: A storage array interconnection fabric may be configured using a torus topology. A storage system including a path-redundant torus interconnection fabric is coupled to a plurality of nodes. The torus interconnection fabric may be configured to connect the plurality of nodes in an array including N rows and M columns, where N and M are positive integers. The array may be configured such that a first node in a first row of the N rows is connected to a second node in the first row and a first node in a first column of the M columns is connected to a second node in the first column. Also an ending node in the first row is connected to the first node in the first row and an ending node in the first column is connected to the first node in the first column. In addition, a first portion of the plurality of nodes is configured to communicate with a plurality of storage devices such as disk drives.

Abstract: A method and computer graphics system capable of super-sampling and performing real-time convolution are disclosed. In one embodiment, the computer graphics system may comprise a graphics processor, a sample buffer, and a sample-to-pixel calculation unit. The graphics processor may be configured to generate a plurality of samples. The sample buffer, which is coupled to the graphics processor, may be configured to store the samples. The sample-to-pixel calculation unit is programmable to select a variable number of stored samples from the sample buffer to filter into an output pixel. The sample-to-pixel calculation unit performs the filter process in real-time, and may use a number of different filter types in a single frame. The sample buffer may be super-sampled, and the samples may be positioned according to a regular grid, a perturbed regular grid, or a stochastic grid.

Abstract: In one aspect, a method for managing program flow in a computer system having a processor having a prefetch mechanism and an instruction pipeline includes providing a set of program instructions having a conditional branch instruction and an system fault-causing instruction, prefetching at least one instruction into the instruction pipeline, the instruction including at least a conditional branch instruction, predicting the outcome of the conditional branch instruction; and prefetching instructions into the instruction queue based upon the result of the predicting step. The branch instruction is configured to direct program flow into or beyond the system fault instruction depending on the result of a predetermined condition.

Abstract: Disclosed is a list editor component for allowing a computer user to arrange a collection of information items. The list editor component displays an editor window that includes a visual representation of a selected arrangement of information items of the collection. The list editor component can receive specification from the user of a new information item to be added to the collection, and user instruction, add the specified new item to the collection. Validation of the new item can be sought prior to adding the item or prior to exporting the item from the list editor component. The editor window can provide a standard graphical user interface responsive to a call from an application program. In one practice, the list editor component limits the application program such that the program cannot substantially vary the presentation of the graphical user interface, or the selected arrangement of information items.

Abstract: Symmetry in a filter is used to reduce the complexity of an interpolator or a decimator and to simplify derivation of resulting discrete samples. In particular, an inverse relationship between weights applied to two samples is recognized and exploited. An inverse relationship is recognized when a first weight is associated with a first of the samples and a second weight is associated with a second of the samples and a weight which is equivalent to the first weight is associated with the second sample and a weight which is equivalent to the second weight is associated with the first sample. The inverse relationship is exploited by forming two composite weights of the first and second weights and weighting composite sample signals with the composite weights. A first of the composite weights has a value which is one-half of the sum of the values of the first and second weights. A second of the composite weights has a value which is one-half of the difference of the values of the first and second weights.

Abstract: A method and mechanism, operating within an application layer of the architectural model of a communications protocol, for maintaining high availability in a computer network utilizing virtual Internet Protocol (IP) addresses. A backup connection is created wherein a second network card is added to a node of a computer network. A failover mechanism operating within the application layer captures an original virtual IP configuration corresponding to a primary network connection of the node and monitors the primary network connection. Upon detecting a failure of the primary network connection, the failover mechanism halts monitoring of the primary connection, captures the current virtual IP configuration of the primary network connection, configures the second network interface with the parameters of the primary network interface, and brings up the second interface. If the current virtual IP configuration was successfully captured, it is used in the configuration of the second interface.

Abstract: In one aspect of the present invention, a method for controlling the operation of a phase locked loop circuit is provided. The method is comprised of monitoring a frequency of a system clock, and a first signal is delivered in response to the detected frequency of the system clock being greater than a preselected setpoint. A second signal is delivered in response to the detected frequency of the system clock being less than a preselected setpoint. A first operating mode of the phase locked loop circuit is selected in response to receiving the first signal. The first mode of operation allows the phase locked loop circuit to synchronize with a clock signal in a first preselected range of frequencies. A second operating mode of the phase locked loop circuit is selected in response to receiving the second signal. The second mode of operation allows the phase locked loop circuit to synchronize with a clock signal in a second preselected range of frequencies.

Abstract: Clocked half-rail differential logic circuits with single-rail logic of the invention do not include complementary logic elements. According to the invention, the complementary logic function of the prior art is replaced by a single transistor appropriately sized to provide the complementary output OUTBAR. Consequently, clocked half-rail differential logic circuits with single-rail logic of the invention use less power and, therefore, generate less heat, require less space, and are simpler in design so that they are more flexible, more space efficient and more reliable than prior art half-rail differential logic circuits.

Abstract: Automated techniques to correct certain rule violations with respect to non-design geometries are used, simplifying and automating the design layout of an electronic circuit, whether embodied as a design encoding or as a fabricated electronic circuit. Adding non-design geometries to a design layout is accomplished by adding one or more non-design geometries to the design layout, the design layout including one or more design geometries; and correcting one or more design rule violations by removing a portion of the one or more non-design geometries; wherein correcting the one or more design rule violations includes: deriving non-design wide class objects from the one or more non-design geometries and design wide class objects from the one or more design geometries; wherein at least one of the non-design wide class objects and the design wide class objects have a virtual edge; and using the virtual edge in determining the portion of the one or more non-design geometries to be removed.

Abstract: Data structures, methods and devices for reducing computing overhead by utilizing different invocation paths for same process and different process invocations in a distributed client/server based computing system are disclosed. In one aspect of the invention, calls to a servant that do not share the same process as the requesting client are routed through a transport layer, and calls to servants that do share the same process as the requesting client are passed directly to the servant, thereby bypassing the transport layer. In another aspect of the invention, distinct remote and local method tables are provided to facilitate intelligent routing of requests. In still another aspect of the invention, the appropriate method table for an object reference is intelligently selected based upon the location of the identified object.

Abstract: Methods and apparatus for executing an applet are disclosed. A virtual machine that includes a class loader generates a file download request in the form of an http request to a particular server computer that contains appropriate applet component files. The class loader queries a root JAR file having an index file associated with applet. The class loader creates a HASH table based upon the contents of the index file that provides a mapping of all packages and all corresponding JAR files required to execute the applet by the virtual machine. During virtual machine runtime the class loader queries the HASH table in order to directly access the appropriate applet component file to be downloaded and executed by the virtual machine.

Abstract: Disclosed herein is a apparatus and method for packing a 16-bit number into an 8-bit result byte. The method and apparatus utilize a parallel processing right shift circuit and a filter to obtain desired results. The parallel processes are comprised of a plurality of multiplexers capable of discretely analyzing smaller groups of bits. In this manner, higher throughput may be obtained than previously known.

Abstract: A processor has an improved architecture for multiple-thread operation on the basis of a highly parallel structure including multiple independent parallel execution paths for executing in parallel across threads and a multiple-instruction parallel pathway within a thread. The multiple independent parallel execution paths include functional units that execute an instruction set including special data-handling instructions that are advantageous in a multiple-thread environment.