Abstract: An invention is provided for an adaptive keeper circuit. The adaptive keeper circuit includes a first keeper transistor having a first terminal in electrical communication with a power supply and a second terminal in electrical communication with an internal dynamic node. In addition, a second keeper transistor is included that is configured in parallel to the first keeper transistor. The second keeper transistor also has a first terminal in electrical communication with the power supply. The second keeper transistor can be added to the first keeper transistor using a feedback bit line, which is configured to control current flow between the second keeper transistor and the internal dynamic node based on a state of the feedback bit line. The state of the feedback bit line is based on a process corner characteristic of the die. Additional keeper transistors and corresponding feedback bit lines can be added to the keeper circuit to increase flexibility.

Abstract: An electronics assembly, for example for use as a network server, comprises a frame that encloses a number of components of the assembly, a facia panel that is attached to a surface of the frame, and is formed as an upper and a lower part that are retained together generally horizontally. The assembly includes a printed circuit board for providing information relating to the assembly, the printed circuit board being located within the facia panel between the two parts. The frame and the fascia panel have a locating element at each side of the fascia panel for ensuring correct positioning of the panel with respect to the frame.

Abstract: An environment is emulated in a host environment. Output generated in the emulated environment is displayed in a window of the host environment. The emulated environment's output is in the form of Postscript commands that map to the entire screen. The host environment emulates the Postscript commands and maps the output to a window. Input associated with the window is retrieved by an event driver running in the host environment. Each instance of input is referred to as an event. Each event is translated into an event of the emulated environment by an event driver. A translated event is stored in shared memory for access by a window server. The event driver notifies the window server that one or more events are queued in shared memory. The window server processes the queued events by, for example, transmitting the event to an application running in the emulated environment.

Abstract: One embodiment of the present invention provides a domino logic circuit that operates asynchronously. This domino logic circuit includes a number of stages, including a present stage that receives one or more inputs from a prior stage and generates one or more outputs for a next stage. It also includes a control circuit that ensures that the present stage enters a precharging state before entering a subsequent evaluation state in which one or more inputs of the present stage are used to generate one or more outputs.

Abstract: A clock detect indicator capable of determining the presence of high and low frequency clock signals is provided. The clock detect indicator, which operates independent of a reference clock, has detection circuitry that determines whether a particular clock signal has alternating high-to-low and low-to-high transitions. Based on the determination, the clock detect indicator outputs a transition on a clock detect indication signal. Further, a method for detecting a clock signal in an integrated circuit is provided.

Abstract: A network proxy is provided that facilitates the integration of orphan services into a network by enabling them to interact with a lookup service that contains an indication of the services that are available on the network. These orphan services typically reside on devices having too little memory to run the components necessary to be integrated into the network. Thus, the network proxy acts as a go between, by registering the orphan services with the lookup service so that clients may access them and by accessing services on behalf of the orphan services. As a result, the network proxy integrates orphan services into the network, when they otherwise would be incapable of doing so.

Abstract: A register file design having an asymmetric bit line driver is provided. More specifically, the register file design uses a memory element that has a footer device that facilitates the discharge/charging of a bit line through a pass device, where a width of the footer device is greater than a width of the pass device. Further, a method for performing low power memory operations using asymmetric bit line drivers is provided.

Abstract: A method and system for performing user-defined code conversions in a computer system. A utility accepts a text file from a user program. This text file contains a series of conditional rules that define a protocol for converting character data between codesets. The utility parses this file and converts it to a binary table format that is then stored in a code conversion table database. The user program then invokes functions contained in the operating system to convert data in accordance with the stored binary table.

Abstract: An IO cell for providing a transmission path for a binary signal. The IO cell includes an IO buffer for amplifying the binary signal. A programmable delay element is electrically connected to the IO buffer such that the binary signal transmits from the programmable delay element to the IO buffer. The delay element is responsive to “n” number of programmable binary bits to selectively delay transmission of the binary signal by a set of predetermined delay time ranges. An IO pad is connected in series with the IO buffer and the programmable delay element.

Abstract: A technique that uses active shields to reduce clock skew is provided. The technique uses a shield wire for shielding the signal wire, a driver stage for driving a leading clock signal on the shielding wire, and a signal wire buffer for driving a lagging clock signal on the signal wire, where the leading clock signal is driven onto the first shield wire a phase difference before the lagging clock signal is driven onto the signal wire.

Abstract: An invention is disclosed for providing methods for parsing test results having diverse formats. Test results from executed test suites are identified. Test result formats of the test results are categorized. An order of the test results is tracked. A chain of parsers is assembled from individual parsers such that each individual parser is charged with parsing a particular test result format. Test results are parsed such that the data features that define attributes of the test results are identified where the attributes define pass, fail, and comments associated with the pass or fail.

Abstract: Custom application development environment modules may be designed to work with a first application development environment. This functionality may be extended to a second application development environment by first creating user interface elements for the second application development environment. User interface elements from the custom application development environment modules may be separated, forming user interface elements for the first application development environment. New general elements may then be created, which are compatible with both the first application development environment and the second application development environment. The general elements may be combined with non-user interface elements from the custom application development environment modules to arrive at a series of generalized classes.

Abstract: An invention is disclosed for a distributed shell for use in a distributed computer environment. The distributed shell includes a shell server, which is located on a server computer system. The shell server processes commands for distribution to particular client computer systems of the distributed computer system. In addition, the distributed shell includes a plurality of shell clients. Each shell client is executed on a separate client computer system and is in communication with the shell server. In operation, the shell server selects a particular shell client to perform a task or tasks in response to receiving a command. The tasks are then sent to the selected shell client and the shell client executes the task.

Abstract: A switching apparatus provides an address extension for an environment, such as I2C, that uses devices with a limited address configurability. The switching apparatus provides connection between a main bus and one or more secondary busses to which additional devices are connected. The switching apparatus detects an address on the main bus, and determines whether it is intended for a device on a secondary bus. If so, it connects the main bus to the proper secondary bus where the device in question is located. It then translates the address to an address within the limited configurability of the devices, and places the translated address on the secondary bus where the addressed device is located.

Abstract: A method of circuit simulation of an overall circuit including at least one nonlinear component and a plurality of fixed linear components. The process begins by obtaining a netlist for the overall circuit. Next, one or more of the individual nonlinear components from the netlist are precharacterized. Generally the precharacterization is performed in advance of the circuit simulation and the results are stored in a table. The overall circuit is broken into one or more subcircuits. The number and size of the subcircuits will depend on the circumstances. The nonlinear components are substituted with equivalent linear components based on the precharacterization. A simulation matrix is built. Generally the matrix is carefully partitioned to reduce the number of calculations. A simulation is run for each of the subcircuits. Finally, the subcircuit simulations are combined to form the overall circuit simulation.

Abstract: The present invention describes a method and an apparatus for waiving noise violations during semiconductor integrated circuit design. The noise violations in a circuit area (e.g., an individual cell, block of cells or the like) are identified using a threshold look-up table. The threshold look-up table includes different thresholds for each circuit area. The threshold look-up table is generated using various cell related information including practical noise handling limits of each cell that can be higher than traditional noise limits. The information in the threshold look-up table helps eliminate benign noise violations and a new noise report is generated. The new noise report incorporates the practical noise handling capabilities of the cell under analysis and identifies actual noise violations in the semiconductor integrated circuit.

Abstract: A method and apparatus are provided for depositing a filler material in a physical layout for an integrated circuit. The filler material is deposited on a layer by layer basis in the physical layout so that a channel length of the filler material has an orientation that differs between immediately adjacent layers. In addition, the filler materials in each of the layers are grouped into a first group and a second group wherein the filler material associated with the first group is coupled to a first portion of a power grid in the integrated circuit and the filler material associated with the second group is coupled to a second portion of the power grid in the integrated circuit. The tiller materials associated with each group are interconnected using one or more vias so that the filler material is capable of expanding the power grid of the integrated circuit to assist in the distribution of power throughout the various layers of the integrated circuit.

Abstract: The present invention describes a method and apparatus for placing flops in a complex circuit design. Initially, the method calculates a physical range for every net that requires a flop, within which the flop can be placed satisfying the timing requirement. After the physical range is defined, the method groups these flops and determines a block where these grouped flops can be placed. Grouping these flops into one block (flop station) can preserve a compact layout for the design. The flops are then connected to appropriate nets.

Abstract: An invention is provided for testing in a Java based environment. The method includes launching a test harness in a first JVM, and starting a virtual machine (VM) agent in a second JVM. The VM agent is placed in communication with the test harness. The VM agent then executes a test application such that both the test application and the VM agent execute in the second JVM. In this manner, the VM agent is restarted using the test harness if the second JVM fails.

Abstract: A circuit reduction method that generates a netlist that maintains a topology of an original circuit while preserving an original circuit's functions and characteristics is provided. Further, a circuit reduction method that allows a user to selectively determine which nodes of an original circuit to reduce is provided. Further, a circuit reduction tool that is capable of removing loops that are not present in an original circuit but are present in an extraction of the original circuit is provided.