Abstract: A circuit reduction method that generates a netlist that maintains a topology of an original circuit while preserving an original circuit's functions and characteristics is provided. Further, a circuit reduction method that allows a user to selectively determine which nodes of an original circuit to reduce is provided. Further, a circuit reduction tool that is capable of removing loops that are not present in an original circuit but are present in an extraction of the original circuit is provided.

Abstract: One embodiment of the present invention provides a system that transmits a stream of datawords through a bundle of conductors with a three-dimensional structure. Upon receiving a dataword to be transmitted, the system uses an encoding function to encode the dataword into a current codeword in a stream of codewords, wherein the current codeword is less than double the size of the dataword. Next, the system transmits the current codeword to a destination through the bundle of conductors. Note that the encoding function depends on a preceding codeword in the stream of codewords, so that when the preceding codeword changes to the current codeword, rising transitions are substantially matched with falling transitions within the bundle.

Abstract: One embodiment of the present invention provides a system that facilitates generating a bus testing data pattern for simultaneously testing multiple bus widths. The system first receives a list of bus widths to be tested. Next, the system receives a root test pattern with a width equal to the width of the smallest bus in the list. The system then inverts each bit of the root test pattern and concatenates this inverted pattern with the original pattern. Next, the system creates an additional pattern by repeating the second pattern sufficient times so that the width of this additional test pattern equals the width of the next larger bus. The system then creates a test pattern for the next larger bus by inverting each bit of the additional test pattern and concatenating this inverted test pattern with the additional test pattern.

Abstract: A merge unit for the merging of tiles or arrays of pixels or samples, and suitable for use in a high performance graphics system is described. The unit may improve the utilization of memory bandwidth by combining non-intersecting tiles of pixels, and hence potentially reducing the number of storage operations to the memory.

Abstract: Network and host efficiencies are improved by reducing the overhead associated with establishing virtual circuits. In one approach, a request for information from a client is sent to a server using a connectionless protocol such as UDP. If the requested information satisfies a policy for return by the connectionless protocol, the response is sent that way. If the policy is not satisfied, the server may reply with a message to try a connection oriented protocol such as TCP. If no response is received at all after a certain number of tries, the client will try a connection using a connection oriented protocol. In a second approach, when a request from a client is sent using a connectionless protocol, the state information for a transaction TCP (T/TCP) connection is set up in the client, giving the server the option of responding either using the connectionless protocol or using T/TCP.

Abstract: A method for optimizing a decoupling capacitance for an on-chip temperature sensor is provided. A representative power supply waveform having noise is input into a simulation of the on-chip temperature sensor; a difference between a temperature representative input and a temperature dependent output of the on-chip temperature sensor is determined; and an amount of the decoupling capacitance is adjusted until the difference falls below a pre-selected value. A computer system for optimizing a decoupling capacitance for an on-chip temperature sensor is also provided. A computer-readable medium having recorded thereon instructions executable by a processor for optimizing a decoupling capacitance for an on-chip temperature sensor is further provided.

Abstract: One embodiment of the present invention provides a system that supports exception handling through use of a conditional trap instruction. The system supports a head thread that executes program instructions and a speculative thread that speculatively executes program instructions in advance of the head thread. During operation, the system uses the speculative thread to execute code, which includes an instruction that can cause an exception condition. After the instruction is executed, the system determines if the instruction caused the exception condition. If so, the system writes an exception condition indicator to a register. At some time in the future, the system executes a conditional trap instruction which examines a value in the register. If the value in the register is an exception condition indicator, the system executes a trap handling routine to handle the exception condition. Otherwise, the system proceeds with execution of the code.

Abstract: A computer system comprising mass storage, a system bus connected to the mass storage, and a processor unit connected to the system bus. A library of standard functions is stored in the mass storage. Each library function is stored in at least one of two versions. The first version is obtained from compilation of firmware code, as is conventional. The second version is obtained from compilation of firmware code and comprises a set of configuration data for loading into a field programmable gate array (FPGA). The computer system is provided with a FPGA connected to the system bus which can be configured by the second versions of the library functions so that these can be performed in the FPGA, instead of in the processor. The apparatus and method are well suited to libraries of database search engine functions. Performance advantages can be obtained by executing function calls in the FPGA.

Abstract: A method and computer system for resolving simultaneous requests from multiple processing units to load from or store to the same shared resource. When the colliding requests come from two different processing units, the first processing unit is allowed access to the structure in a predetermined number of sequential collisions and the second device is allowed access to the structure in a following number of sequential collisions. The shared resource can be a fill buffer, where a collision involves attempts to simultaneously store in the fill buffer. The shared resource can be a shared write back buffer, where a collision involves attempts to simultaneously store in the shared write back buffer. The shared resource can be a data cache unit, where a collision involves attempts to simultaneously load from a same data space in the data cache unit.

Abstract: The present invention provides a verifier for use in conjunction with programs utilizing data type specific bytecodes for verifying the proper operation of the executable program prior to actual execution by a host processor. A verifier is provided which includes a virtual stack for temporarily storing stack information which parallels the typical stack operations required during the execution a bytecode program. The verifier also includes a stack snapshot storage structure having a snapshot directory and stack snapshot storage area for storing the state of the virtual stack at various points during program verification so as to assure proper stack manipulations by the source program. A two step source program verification process is provided for in which the source program is initially loaded into the verifier and a first pass source program evaluation is performed.

Abstract: In accordance with the present invention a process is provided for allocating and deallocating resources in a distributed processing system having a requester platform and a server platform. The process involves receiving a request from the requester platform referring to a system resource and specifying a requested lease period, permitting shared access to the system resource for a lease period, sending a return call to the requester platform advising of the lease period, and deallocating the system resource when the lease period expires.

Abstract: Clocked full-rail differential logic circuits with sense amplifier and shut-off are activated by a delayed clock and include a sense amplifier circuit that is triggered by a second delayed clock and a shut-off device. The addition of the sense amplifier circuit, and second delayed clock signal allows the sense amplifier circuit to act as the driver and therefore there is no need for increasing the size of the differential logic network to provide a driver function. The addition of the shut-off device provides a full-rail differential logic circuit with shut-off that does not experience the large “dip” experienced by prior art full-rail differential logic circuits and is therefore more power efficient.

Abstract: A method is provided, the method comprising testing at least one hot-pluggable peripheral hardware device and a computer system by simulating hot-plugging the at least one hot-pluggable peripheral hardware device using a test fixture inserted between the computer system and the at least one hot-pluggable peripheral hardware device. The method also comprises monitoring at least one effect of testing the at least one hot-pluggable peripheral hardware device and the computer system.

Abstract: PCI load/store operations and DMA operations are implemented via work queue pairs in a message-passing, queue-oriented bus architecture. PCI address space is divided into segments and, each segment, in turn, is divided into regions. A separate work queue is assigned to each segment. A first portion of a PCI address is matched against the address ranges represented by the segments and used to select a memory segment and its corresponding work queue. An entry in the work queue holds a second portion of the PCI address which specifies a region within the selected segment that is assigned to a specific PCI device. In one embodiment, PIO load/store operations are implemented by selecting a work queue assigned to PIO operations and creating a work queue entry with the PCI address of a register on a PCI device and a pointer to the PIO data. The work queue entry is sent to a PCI bridge where the PCI address is extracted and used to program the appropriate device register with the data using the data pointer.

Abstract: One embodiment of the present invention provides a system for facilitating speculative store operations in a multiprocessor system. This system operates by maintaining a record of speculative store operations that are in process at an L2 cache in the multiprocessor system, wherein a speculative store operation is a store operation that is speculatively executed before a preceding store operation has returned. Upon receiving a load operation at the L2 cache from an L1 cache, the system examines the record of speculative store operations to determine if there exists a matching speculative store operation that is directed to the same location that the load operation is directed to. If so, the system ensures that the load operation takes place after the matching speculative store operation completes.

Abstract: Techniques for performing static binding of dispatched-calls in the presence of dynamic linking and loading are provided. A method for increasing the execution performance of a function at run-time includes compiling the function, which may either be interpreted or previously compiled, and identifying a call within the function to a process. The method also includes adding dependency information to the function. The dependency information is arranged to indicate a status of the function, and contains information pertaining to the class, the name, and the signature associated with the process. In one embodiment, the process is a virtual process, and the method includes analyzing a class structure associated with the function in order to determine when the virtual process is a substantially unique target of the call. In such an embodiment, the virtual process may be inlined into the function when it is determined that the virtual process is the substantially unique target of the call.

Abstract: A power dissipation control mechanism for a central processing unit includes a power estimation circuit for estimating the power dissipation of instructions executed by the central processing during a selected time interval and a speed controller for adjusting the speed of the central processing unit in response to the estimated power dissipation produced by the power estimation circuit.

Abstract: A thin-client device having an application program obtains a copy of an application update having an update barrier level via a network. The thin-client device receives a set of configuration parameters from a configuration server via the network and sets the barrier level value to a value specified by the set of configuration parameters. Alternatively, the thin-client device retrieves a default barrier level value stored in the thin-client device. If the set of configuration parameters does not specify a barrier level value, the barrier level value is set to the default barrier level value. The thin-client device compares the update barrier level to a barrier level value corresponding to a minimum application version necessary to maintain support for a critical feature. If the update barrier level is greater than or equal to the barrier level value, the thin-client device updates its application program.

Abstract: Disclosed is an input/output (IO) device having a power supply node, an input node for receiving an input data signal, and an output node for outputting an output data signal generated in response to the input node receiving the input data bit signal. The IO device also includes a pull-up driver coupled to the power supply node and the output node, wherein the pull-up driver comprises an impedance at the output node which is constant for all voltages at the output node. Additionally, the IO device may have a circuit coupled to the input node, the pull-up driver, and the output node. This circuit is configured to generate a signal that is provided to the pull-up driver. The signal generated by the circuit varies as a function of the voltage at the output node.

Abstract: A method, computer program, signal transmission and apparatus pre-verify instructions in a module of a computer program one module-at-a-time. First it is determined whether checking an instruction in a first module which is loaded requires information in a referenced module different than the first module. If the information is required, a constraint for the referenced module is written without loading or otherwise accessing the referenced module. During linking it is determined whether a first module which is loaded has passed pre-verification one-module-at-a-time before linking. A pre-verification constraint on a constrained module is read, if any, if the first module has passed such verification. If any pre-verification constraint is read, the pre-verification constraint is enforced if the constrained module is already loaded.