Abstract: A adjustment and calibration system for reducing an impedance of a power supply path of an integrated circuit is provided. The power supply path includes a first power supply line and a second power supply line to provide power to the integrated circuit. At least a digital potentiometer connected between the first power supply line and the second power supply line is adjusted to reduce the impedance of the power supply path. Control information, representative of a desired value for the digital potentiometer, is stored in a storage device. The control information stored in the storage device is subsequently selectively read out in order to adjust the digital potentiometer to a state corresponding to the control information.

Abstract: A temporal delay circuit for synchronizing a source synchronous input with a local clock is provided. The source synchronous input comprises a data input and a source synchronous clock. The temporal delay circuit includes a temporal delay queue, a write pointer arranged to write the data input to the temporal delay queue based on the source synchronous clock, and a read pointer synchronized with the local clock and arranged to read from the temporal delay queue according to a desired delay.

Abstract: A method of creating a black box timing model for a digital circuit. The digital circuit is characterized by a block model having at least one input and at least one output. The method determines a delay statement for the output of the block model. The method also determines an input set-up constraint for the input of the block model. The input set-up constraint is based upon the delay statement. The model is then used with a static timing analyzer to accurately model a flow-through circuit.

Abstract: Clocked full-rail differential logic circuits with shut-off include a shut-off device. The addition of the shut-off device provides a full-rail differential logic circuit with shut-off that does not experience the “dip” experienced by prior art full-rail differential logic circuits and is therefore more power efficient. In addition, the present invention provides a full-rail differential logic circuit with shut-off that is more resistant to noise than prior art full-rail differential logic circuits.

Abstract: A server for a thin client network comprises a thin client network management and control module. The server also comprises a network interface mechanism which includes a broadband interface module and a narrowband emulation module inter-operable to provide a communications link to one or more thin client terminals on the thin client network. The management and control module is inter-operable with the network interface mechanism for providing a thin client network over a broadband network. Broadly speaking, the narrowband emulation module is superimposed on the broadband interface module to provide a network interface mechanism operable as an emulated narrowband interface. A thin client network implemented over a broadband network is also disclosed, together with a method for setting up and operating the same.

Abstract: Clocked half-rail differential logic circuits with sense amplifier and shut-off are activated by a delayed clock and include a sense amplifier circuit that is triggered by a second delayed clock and a shut-off device. The addition of the sense amplifier circuit, and second delayed clock signal allows the sense amplifier circuit to act as the driver and therefore there is no need for increasing the size of the differential logic network to provide a driver function. The addition of the shut-off device provides a half-rail differential logic circuit with shut-off that does not experience the large or “dip” experienced by prior art half-rail differential logic circuits and is therefore more power efficient.

Abstract: Clocked full-rail differential logic circuits with sense amplifier and shut-off are activated by a delayed clock and include a sense amplifier circuit that is triggered by a second delayed clock and a shut-off device. The addition of the sense amplifier circuit, and second delayed clock signal allows the sense amplifier circuit to act as the driver and therefore there is no need for increasing the size of the differential logic network to provide a driver function. The addition of the shut-off device provides a full-rail differential logic circuit with shut-off that does not experience the large “dip” experienced by prior art full-rail differential logic circuits and is therefore more power efficient.

Abstract: Methods and systems for protecting object identity in an object-oriented programming language. An object from a class for protecting object identity is instantiated in memory. The object includes a first method that determines whether two object values are equal, and a second method that overrides an identity method associated with a superclass of the object by invoking the first method, the identity method for determining the identity of two objects. The object is immediately locked in response to the instantiating, so that the identity of the locked object is protected from threads that attempt to synchronize on the locked object.

Abstract: An aspect of the current invention is directed to a method for modeling behavior of a non-linear component with a first interconnect line in a system of a plurality of interconnect lines. The method contemplates modeling an interconnect lines as a plurality of segments. Each of the segments of the interconnect line are coupled together to form the interconnect line. A non-linear component is modeled as coupled to a line segment. The line segment has an electric coupling to the other line segments, possibly on different interconnect lines. A signal associated with the first interconnect line is precharacterized. The signal is indicative of the output of the non-linear component on the line segment. The signal is then input into a linearized simulation of the system of interconnect lines.

Abstract: Clocked full-rail differential logic circuits are provided with shut-off devices. The addition of the shut-off device provides a full-rail differential logic circuit with shut-off that does not experience the large pre-charge high or “dip” experienced by prior art full-rail differential logic circuits and is therefore more power efficient. In addition, the present invention provides a full-rail differential logic circuit with shut-off that is more resistant to noise than prior art full-rail differential logic circuits.

Abstract: A computer system, for example a network server, comprises a service processor for providing system management functions for the system, and at least one peripheral component that communicates with, and/or is controlled by, the service processor via a communication or control line. The system includes a timer that is initialised by the service processor at a predetermined rate. If the timer is not initialised within a certain time period, it will reset the peripheral device to a different state, e.g. a quiescent state or one that is independent of the service processor. The timer is separate from the service processor and the service processor sends initialisation signals to the timer along the communication or control line.

Abstract: A method and apparatus for detecting leading zeros in a number represented by a plurality of four-bit nibbles, each nibble having an associated order of significance, said method comprising is disclosed. The leading zero detector calculates a leading zero count for each nibble in parallel, associates with each nibble count calculation a bit value inversely corresponding to the nibble's order of significance, and selects the nibble count calculation which corresponds to the highest order nibble without all zero values.

Abstract: A method for enabling an application program to communicate with a network server, includes the steps of downloading a document from a document server to the application program, downloading code from a code server associated with the document server to the application program, the code including a network protocol handler for the network server, and using the network protocol handler to communicate with the network server.

Abstract: Several methods are described for building and using a network device database. The network includes multiple enclosures, and each enclosure houses at least one device (e.g., a data storage device). The network may be, for example, a storage area network. One embodiment of a method for deriving the addresses of all devices of the network includes repeating the following steps for each enclosure of the network. A command is issued to the enclosure requesting information comprising device identifications (IDs) of all devices within the enclosure. A portion of an address of the enclosure is concatenated with each device ID to form the addresses of all devices within the enclosure. The network may include one or more Fibre Channel Arbitrated Loops (FC-ALs). In this case, the addresses of the enclosures and the devices coupled FC-ALs are fabric addresses. Each enclosure may include a small computer system interface (SCSI) enclosure services (SES) unit.

Abstract: A mutual exclusion arrangement is disclosed for use in connection with a computer, the computer being configured to execute at least one program having at least one thread in a series of time slots. The mutual exclusion arrangement includes, associated with the computer, a signal generator and, associated with the at least one thread, a signal handler. The signal generator is configured to generate a signal for provision to the at least one thread when the computer initiates processing of the at least one thread in one of the time slots. The signal handler is configured to, in response to the signal, determine whether the thread, when it begins execution in the time slot, will be executing a section of code that is to be executed in an atomic manner, and, if so, enable the thread to begin execution at a beginning of the section, and otherwise enable the thread to begin execution subsequent to previously-executed code.

Abstract: System and method for caching JavaServer Page™ (JSP) component responses. The JSP components may be components that execute on an application server that supports networked applications, such as web applications or other Internet-based applications. One or more client computers, e.g., web servers, may perform requests referencing the JSP components on the application server. The execution of JSP components may be managed by a JSP engine process running on the application server. When a request referencing a JSP is received from a client computer, the JSP engine may first check a JSP response cache to determine whether a valid JSP response satisfying the request is present. If a matching cached response is found, then the response may be retrieved and immediately streamed back to the client. Otherwise, the referenced JSP may be executed. Each JSP file may comprise various SetCacheCriteria( ) method calls.

Abstract: Several systems and methods are described for accessing one of multiple groups of peripheral devices. One of the systems includes a host system, multiple peripheral devices, and a host adapter. The peripheral devices are arranged to form multiple groups, each group including at least one peripheral device. The host system is coupled to the peripheral devices via the host adapter, and accesses the peripheral devices via the host adapter. The peripheral devices of each group receive a group access signal for controlling accesses from the host system. The host adapter includes a control register and signal routing logic. The signal routing logic is coupled to the control register and to each of the groups of peripheral devices. The control register stores a value for selecting one of the groups of peripheral devices. The host system may include a central processing unit (CPU) configured to write the value to the control register.

Abstract: A clock interpolation circuit for setting and controlling a phase of an output clock that is derived from an interpolation of multiple input clocks. Interpolation is performed by capacitively weighting the multiple clocks. A select and control circuit provides the ability to select different capacitance values to control the weighting. An optional buffer stage is also provided to sharpen the edge transitions of the interpolated clock.

Abstract: The present invention provides a solution for converting a boundary scan description language (BSDL) file to a hardware verification language (HVL) test program file. The BSDL file is scanned for header information and the header information is stored in a header object. The BSDL file is then scanned for pin information, the pin information corresponding to at least one pin in the BSDL file having a pin location, and stored in a pin object. At least one variable for the HVL test program file is created and bound to one of the pin locations resulting in a binding relationship for each variable. The binding relationships are then stored in a bind object. The present invention is designed to overcome the disadvantages of the prior art.