Abstract: A method, computer program, signal transmission and apparatus pre-verify instructions in a module of a computer program one module-at-a-time. First it is determined whether checking an instruction in a first module which is loaded requires information in a referenced module different than the first module. If the information is required, a constraint for the referenced module is written without loading or otherwise accessing the referenced module. During linking it is determined whether a first module which is loaded has passed pre-verification one-module-at-a-time before linking. A pre-verification constraint on a constrained module is read, if any, if the first module has passed such verification. If any pre-verification constraint is read, the pre-verification constraint is enforced if the constrained module is already loaded.

Abstract: The present invention provides methods and apparatus for a computer network system to provide compact and efficient representations of graphics commands on drawing/displaying lines, circles, etc. The methods and apparatus exploit the redundancies and/or relations of the information in drawing/displaying lines, circles, etc. and allow for fewer bytes and faster transmission rate (e.g., more graphics primitives per second) to a client tier (e.g., to a thin client appliance and/or a display on the desktop appliance). For example, one embodiment of the present invention uses commands that take advantage of the structure of spans created by drawing commands to send a base fill command, followed by fills whose locations and size are expressed as deltas with respect to each previous fill in the list. The deltas may comprise a difference between two commands, a difference between a command and another difference, a difference between two differences, and/or a plurality of differences.

Abstract: Clocked half-rail differential logic circuits with single-rail logic and sense amplifier of the invention do not include complementary logic elements. According to the invention, the complementary logic function of the prior art is replaced by a single transistor appropriately sized to provide the complementary output. In addition, the clocked half-rail differential logic circuits are activated by a delayed clock and include a sense amplifier circuit that is triggered by a second delayed clock. The addition of the sense amplifier circuit, and second delayed clock signal, allows the sense amplifier circuit to act as the driver and therefore there is no need for increasing the size of the differential logic block to provide a driver function.

Abstract: Clocked half-rail differential logic circuits with single-rail logic of the invention do not include complementary logic elements. According to the invention, the complementary logic function of the prior art is replaced by a single transistor appropriately sized to provide the complementary output OUTBAR. Consequently, clocked half-rail differential logic circuits with single-rail logic of the invention use less power and, therefore, generate less heat, require less space, and are simpler in design so that they are more flexible, more space efficient and more reliable than prior art half-rail differential logic circuits.

Abstract: In an embodiment, the present invention describes a method and apparatus for detecting RAW condition earlier in an instruction pipeline. The store instructions are stored in a special store bypass buffer (SBB) within an instruction decode unit (IDU). The IDU compares the instruction fields that are used for address generation of all ‘load’ instructions against ‘store’ instructions within a group of fetched instructions and ‘store’ instructions previously stored in the SBB. If a match of instruction fields is found, the IDU ‘speculates’ that the load instruction has dependency on the ‘store’ instruction. A data cache unit (DCU) validates the dependency of the load instruction ‘speculated’ by the IDU. If a false dependency is ‘speculated’ by the IDU, the DCU forces a re-fetch of the load instruction.

Abstract: A thin-client device broadcasts a configuration request message over a network. In response to the configuration request message, the thin-client device receives a configuration response message including a first set of configuration information. The thin-client device determines if the configuration response message includes a second set of configuration information. If the configuration response message does not include the second set of configuration information, the thin-client device broadcasts a status message over a network. In response to the status message, the thin-client device receives a status response message with the second set of configuration information.

Abstract: Methods and apparatus for providing customized security and logging protocols in a servlet environment are described. A servlet engine that includes a security module that assures that only those requests that are properly authenticated and authorized are serviced by a servlet. A logging module provides customized records of both security module and servlet transactions.

Abstract: Methods and apparatus for loading and unloading classes associated with an application are disclosed. A class loader adapted for loading classes associated with an application is constructed. The class loader is employed to load one or more classes associated with the application such that the class loader maintains a reference to the one or more classes. The class loader for the application is then de-referenced such that the class loader is unreachable.

Abstract: In embodiments of the invention, a method and apparatus for dynamic proxy insertion in network traffic path is described. According to one or more embodiments of the invention, a request and/or response message may be modified to include one or more thru-proxy tags to identify a network (or traffic) node (e.g., a proxy, server, or intermediary). For example, a request directed to a server or a response directed to a client may be altered to insert a plurality of intermediate or final destination designations. In so doing, a path of a request or response may be altered dynamically. A thru-proxy tag in a response may be inserted in a related request to identify a destination or node such that the request is sent to the destination in the thru-proxy tag before being sent to an origin server. Thru-proxy tags may be used to identify multiple and/or alternate destinations.

Abstract: A novel FIFO data structure in the form of a multi-dimensional FIFO. For a rectangular multi-dimensional FIFO, data items are received at an input of an N-row-by-M-column FIFO array of cells and transferred to an output, via a predetermined protocol of cell transfers, in the same order as received. Transfer rules or protocol are controlled by a control circuit implemented using asynchronous pipeline modules or a control circuit relying upon transition signaling.

Abstract: One embodiment of the present invention provides a multiprocessor system that supports multiple cache line invalidations within the same cycle. This multiprocessor system includes a plurality of processors and a lower-level cache that is configured to support multiple concurrent operations. It also includes a plurality of higher-level caches coupled to the plurality of processors, wherein a given higher-level cache is configured to support multiple concurrent invalidations of lines within the given higher-level cache. In one embodiment of the present invention, the lower-level cache includes a plurality of banks that can be accessed in parallel to support multiple concurrent operations. In a variation on this embodiment, each line in a given higher-level cache includes a valid bit that can be used to invalidate the line. These valid bits are contained in a memory that is organized into a plurality of banks that are associated with the plurality of banks of the lower-level cache.

Abstract: One embodiment of the present invention provides a domino logic circuit that operates asynchronously. This domino logic circuit contains a pipeline comprised of a number of stages of domino logic, including a present stage that receives one or more inputs from a prior stage and that generates one or more outputs for a next stage. The present stage includes a control circuit that is configured to ensure that the present stage enters a precharging state before entering an evaluation state—in which one or more inputs of the present stage are used to generate one or more outputs. This control circuit operates by receiving a prior control signal from the prior stage and sending a present control signal to the next stage. During this process, the control circuit ensures that a minimum cycle time between successive evaluation states is six gate delays.

Abstract: A phase locked loop circuit is provided. The phase locked loop circuit is comprised of a first and second divide-by-N counter, a phase comparator, a voltage controlled oscillator, a clock tree, and a feedback path. The first divide-by-N counter is adapted to receive a first clock signal and provide a second clock signal. The phase comparator has a first and second input terminal and an output terminal. The phase comparator is adapted to compare the phase of signals applied to the first and second input terminals and deliver a signal at the output terminal having a magnitude indicative of a difference in the phases of the signals. The first input terminal is coupled to receive the second clock signal. The voltage controlled oscillator is coupled to receive the phase difference signal and deliver a third clock signal having a frequency responsive thereto. The second divide-by-N counter is coupled to receive the third clock signal and deliver a fourth clock signal.

Abstract: One embodiment of the present invention provides a system that facilitates sampling a cache in a computer system, wherein the computer system has multiple central processing units (CPUs), including a measured CPU containing the cache to be sampled, and a sampling CPU that gathers the sample. During operation, the measured CPU receives an interrupt generated by the sampling CPU, wherein the interrupt identifies a portion of the cache to be sampled. In response to receiving this interrupt, the measured CPU copies data from the identified portion of the cache into a shared memory buffer that is accessible by both the measured CPU and the sampling CPU. Next, the measured CPU notifies the sampling CPU that the shared memory buffer contains the data, thereby allowing the sampling CPU to gather and process the data.

Abstract: A method for reducing noise in an I/O system has been developed. The method includes powering up the I/O supply and activating or inserting a shunting resistance across the power supply terminals. The shunting resistance is inserted in parallel with the I/O power supply, and is controllable such that the resistance can be selectively switched ‘on’ and/or ‘off.

Abstract: One embodiment of the present invention provides a system for testing a computer system by using software to inject faults into the computer system while the computer system is operating. This system operates by allowing a programmer to include a fault point into source code for a program. This fault point causes a fault to occur if a trigger associated with the fault point is set and if an execution path of the program passes through the fault point. The system allows this source code to be compiled into executable code. Next, the system allows the computer system to be tested. This testing involves setting the trigger for the fault point, and then executing the executable code, so that the fault occurs if the execution path passes through the fault point. This testing also involves examining the result of the execution.

Abstract: A mechanism for enabling customized session managers to interact with a network server is disclosed. The mechanism includes a programming interface which enables customized session managers to “plug in” to and to interact with the server. This programming interface makes it possible to change session management functionality without having to make any changes to the core server. It also makes it possible to incorporate multiple session managers into the server. These aspects of the programming interface significantly increase the flexibility and scalability of the web server. In addition to the programming interface, the mechanism further includes a service engine for coordinating the interaction with the session managers. For each client request, the service engine determines which application needs to be invoked. Then, based upon that application, the service engine determines which, if any, associated session manager needs to be invoked to manager session (i.e.

Abstract: Disclosed is an input/output (IO) device for transmitting a data bit signal. In one embodiment, the IO device includes an IO device input node for receiving an input data bit signal and an IO device output node. Additionally, the IO device includes a plurality of drivers coupled between the IO device input and output nodes, each having first and second n-channel FETs coupled together, first and second p-channel FETs coupled together. A drain of each driver's second n-channel FET and each driver's first p-channel FET is coupled to the IO device output node, while a gate of each driver's first n-channel FET is coupled to the IO device input node.

Abstract: A adjustment and calibration system for reducing an impedance of a power supply path of an integrated circuit is provided. The power supply path includes a first power supply line and a second power supply line to provide power to the integrated circuit. At least a digital potentiometer connected between the first power supply line and the second power supply line is adjusted to reduce the impedance of the power supply path. Control information, representative of a desired value for the digital potentiometer, is stored in a storage device. The control information stored in the storage device is subsequently selectively read out in order to adjust the digital potentiometer to a state corresponding to the control information.

Abstract: A thermal storage device for maintaining the temperature of an article at a desired temperature for a length of time comprises a compartment within which the article may be positioned, an evaporator which is disposed in heat exchange relation with respect to the compartment, a receiver which is fluidly connected to the evaporator, a sorber which is fluidly connected between the evaporator and the receiver and which includes a sorbent that is capable of adsorbing a refrigerant, a desorbing device for desorbing the refrigerant from the sorbent, and a power connection device for releasably connecting an external power supply to the desorbing device. When the desorbing device is connected to the external power supply, the refrigerant is desorbed from the sorbent and communicated to the receiver.