Abstract: A method and apparatus for compensating for gate current through a first capacitor includes: a biasing circuit; a first compensation transistor; a second compensation transistor; and a compensation capacitor. The biasing circuit ensures the bias voltage across the compensation capacitor is equal to the bias voltage across the first capacitor. In addition, the size of the second compensation transistor is chosen such that if, the ratio of the area of the compensation capacitor divided by the area of the first capacitor is area ratio “AR”, then, the ratio of the size of first compensation transistor divided by the size of second compensation transistor is also area ratio “AR”. As a result, according to the method and apparatus of the present invention, the gate current Ig through the first capacitor is equal to the current drained off through second compensation transistor.

Abstract: A method and apparatus for managing relationships among objects in a distributed object environment includes a method and apparatus for determining whether two or more object references refer to identical objects; a method and apparatus for providing a unique identifier for an object; a method and apparatus for checking role types for the formation of relationships; and a method and apparatus for caching role and object locations in roles in a relationship. In the method and apparatus for determining whether two or more object references refer to the same object, a unique object identifier is compared to determine if the objects referred to by the object references are identical. The unique identifier is provided by concatenating information identifying the machine address of the process that created the object in addition to the process ID, the time of creation and a process counter.

Abstract: A computer-based method for improved automatic formatting of a document provides easier accepting and rejecting of formatting actions made by the automatic formatting method. In particular, the user inputs a document, or any part of a document, into a computer system. For each document portion that the user wants formatted in a particular way, the user delimits that portion of the document with a unique format identification feature that corresponds to a format rule. When the user initiates the computer-based automatic formatting method, the method identifies each document portion in the document delimited by at least one format identification feature, and applies to that document portion a format rule corresponding to the at least one format identification feature. The method displays an indicium of the format rule together with the document portion thereby displaying the format rule and the document portion together. The method then receives a user input accepting or rejecting the displayed format rule.

Abstract: An interconnect structure includes a signal wire and an active shield line adjacent to, but removed from, the signal wire. The interconnect structure also includes another active shield line adjacent to, but removed from, the signal wire. A signal driver is connected to the signal wire. The signal driver drives a pulse on the signal wire. A shield driver is connected to the active shield line. The shield driver asserts a signal on the active shield line substantially simultaneous with the pulse. Another shield driver is connected to the another active shield line. The another shield driver asserts a signal on the another active shield line substantially simultaneous with the pulse. The effect of the simultaneous signals on the signal wire and the active shield lines is to effectively cancel the lateral capacitances between these lines.

Abstract: An electronics module comprises a housing; and a plurality of electronic and electrical components for example fans. The module includes electromagnetic shielding for example perforated panels side walls etc. that is associated with the housing and/or the electronic components, and which provides a Faraday cage for the electronic components. The shielding is constructed so that one or more of the components can be removed from the module while the module is in operation substantially without affecting the integrity of the Faraday cage. The module enables certain components thereof to be replaced without adding to the downtime of the system or increasing electromagnetic interference.

Abstract: An invention is provided for affording thread priority control in a distributed computer system. At least one task is executed on a server, where each task includes a task identifier and a priority value. In addition, a change priority message, which includes priority value and a task identifier, is received over a network. In response, the priority value of a specific task having the same task identifier as the task identifier of the change priority message is set equal to the priority value of the change priority message. As a result, the specific task is executed at a priority level relative to the priority value of the specific task.

Abstract: We present a technique for implementing obstruction-free atomic multi-target transactions that target special “transactionable” locations in shared memory. A programming interface for using operations based on these transactions can be structured in several ways, including as n-word compare-and-swap (NCAS) operations or as atomic sequences of single-word loads and stores (e.g., as transactional memory).

Abstract: The present invention provides a method and apparatus for increasing availability of an application during fail-back from a secondary site to a primary site following a failure at the primary site. The method includes copying data from active storage volumes to secondary storage volumes of the secondary site while the application runs on the secondary site and updates the active storage volumes. Once the secondary storage volumes of the secondary site are updated, the data is re-synchronized from the secondary storage volumes of the secondary site to the primary storage volumes of the primary site. The steps of copying the data and resynchronizing the data are repeated for data updated by the application, during the resynchronization, until a time required to complete the resynchronization step for the updated data is within an acceptable downtime for the application. Once this step is complete, the application is failed-back to the primary site by bringing up the application at the primary site.

Abstract: A circuit board mount is provided for mounting a circuit board in an electronic equipment housing. The mount is mountable on a surface within the housing and includes a slot for receiving and supporting the circuit board at a first height with respect to the housing surface. The mount further comprises at least one upstand of a second height higher than that of the circuit board, whereby a component can be supported on the upstand without contacting the circuit board. The mount is thus able to support the circuit board and to protect the circuit board during handling of other components within the housing.

Abstract: Provided is a data structure containing wiring information for an integrated circuit and a method for storing the same in a computer readable medium. In one embodiment of the present invention storage of the data structure is achieved by mapping said integrated circuit into memory locations of said medium as a wiring plane having a plurality of data points arranged in a grid. Each of the plurality of data points having state information associated therewith, which includes a plurality of attributes. Subsections of the grid are associated with memory locations in the computer readable medium to form a plurality of tiles. Specifically the tiles and data points are arranged so that a sub-portion of the data points associated with one of the plurality of tiles have common attributes.

Abstract: The present invention provides an apparatus for booth decoding which stores the most significant bit of the lower half of the number used as the key for booth decoding. By using this stored bit to determine the rightmost booth group corresponding to the upper half of the key, booth decoding may be accomplished more quickly using an apparatus that is simpler and smaller than prior art assemblies.

Abstract: The present invention discloses improved heatsink designs and methods for cooling a heat source. One embodiment is a heatsink assembly for removing heat from an electronic component, the heatsink assembly comprising a copper-based core section having a first surface generally adapted to conform to an exposed mating surface of an electronic device and a second surface having a generally convex curvature having a greater surface area than the first surface. An aluminum-based outer section has a first surface comprising a concave curvature that is generally adapted to conform to the convex curvature of the core and a second surface. A plurality of fin elements protrude outwardly from the second surface of the outer section. At least one cooling fan can be positioned to direct airflow onto the fin elements. The core section can comprise a semi-spherical shape and can be joined by a finger-joint type connection to the outer section.

Abstract: The present invention provides a method and apparatus for data flow control. One embodiment detects input congestion and output starvation in a plurality of sub-buffers of a ripple FIFO buffer. This embodiment is used to draw conclusions about the occupancy of the ripple FIFO buffer under steady-state conditions. One embodiment detects input congestion and output starvation at every sub-buffer of the ripple FIFO buffer. Other embodiments detect input congestion and output starvation at a subset of the sub-buffers of the ripple FIFO buffer. One embodiment determines occupancy of the ripple FIFO buffer by the number of sub-buffers which report a steady congested state. Another embodiment determines occupancy of the ripple FIFO buffer by the number of sub-buffers which report a steady starved state. Another embodiment determines occupancy of the ripple FIFO buffer by the location of sub-buffers which report a steady congested state.

Abstract: A technique for verifying decoupling capacitance using a maximum flow determination is provided. The technique involves generating a network representing decoupling capacitors and driver elements on an integrated circuit, selectively establishing connections between decoupling capacitors and driver elements, and determining a maximum flow of the network. Using the maximum flow of the network, a designer may then verify whether particular driver elements are receiving sufficient decoupling capacitance and whether particular decoupling capacitors are being used efficiently, and subsequently redesign an integrated circuit as deemed necessary.

Abstract: A method and apparatus for providing distributed clip-list management. In an embodiment, an application maintains a local clip-list that identifies those portions of a remote frame buffer that are unambiguously associated with the given application, as well as those portions of the remote frame buffer which are disputed between the given application and one or more other applications. Applications may enforce a dispute policy with respect to writing image data to disputed regions of the frame buffer. Applications are able to write to the frame buffer asynchronously, without the use of a frame buffer lock. A clip manager maintains a global clip-list, and responds to messages from the applications by updating the global clip-list and informing those other applications of relevant changes to their own respective local clip-lists.

Abstract: A processor includes logic for attaining a very fast exception handling functionality while executing non-threaded programs by invoking a multithreaded-type functionality in response to an exception condition. The processor, while operating in multithreaded conditions or while executing non-threaded programs, progresses through multiple machine states during execution. The very fast exception handling logic includes connection of an exception signal line to thread select logic, causing an exception signal to evoke a switch in thread and machine state. The switch in thread and machine state causes the processor to enter and to exit the exception handler immediately, without waiting to drain the pipeline or queues and without the inherent timing penalty of the operating system's software saving and restoring of registers.

Abstract: A central processing unit (CPU) is provided and is coupled to a display for displaying graphic and other data in multiple overlapping windows. The CPU is further coupled to one or more input devices which permits a user to selectively position a cursor and input and manipulate data within each of the windows on the display. The windows include defined areas having window features such as text, icons and buttons corresponding to functions to be executed by the CPU. Multiple applications may be executed concurrently by the CPU such that each application is associated with one or more windows. Each display element (“pixel”) comprising the display is represented by multiple bits in a computer frame buffer memory coupled to the CPU. An alpha value (&agr;) is associated with the intensity of each pixel of the display, such that multiple images may be blended in accordance with a predefined formula utilizing the alpha values.

Abstract: A system and method for delivering parking information is disclosed. Embodiments of the present claimed invention utilize video imaging to analyze the availability of parking spaces. More specifically, a computer is used to process video images of a parking location to determine if a parking space is available.