Abstract: A scalable cluster system that provides scalable services for client applications is provided with client affinity. The scalable services are transparent to the client application. To facilitate this transparent scalability, the system provides different types of client affinity to different services for the client applications. Services may have no client affinity, so that different packets sent during different connections could be sent to different nodes on the cluster. Services may have single service client affinity, which causes packets for a single service from different connections from the same source to be sent to the same node. Services may have multiple service client affinity, which causes packets for different services from different connections from the same source to be sent to the same node. Services may have wild card client affinity, which causes packets for different destination ports from different connections from the same source to be sent to the same node.

Abstract: A method of integrating a heat spreader into a semiconductor package includes depositing an adhesion metal layer on the back of a wafer at low temperature. A heat transfer metal layer is subsequently deposited on the adhesion metal layer at low temperature to form a heat spreader.

Abstract: The illustrated embodiment of the present invention provides an efficient means of obtaining traffic information selectively tailored to a motor vehicle's current location. It allows additional detail to be transmitted to the occupant of a motor vehicle as a result of a smaller geographic area being reported. The use of the current motor vehicle location allows the present invention to omit extraneous information that is of limited interest to the occupant of the motor vehicle because it is outside the intended path of travel. The illustrated embodiment also allows for a dynamic real time updating of traffic conditions as they change over the course of time.

Abstract: An invention for an application launcher testing system is provided. The system includes an HTTP server that is in communication with an application launcher, and receives a query for a test application from the application launcher. A status server is also included that is in communication with the test application. The status server receives a test status from the test application. Further, the system includes a test monitor that is in communication with the HTTP server and the status server. The test monitor receives a query status from the HTTP server and the test status from the status server.

Abstract: An invention is provided for reducing cache conflict misses via specific placement of non-split functions and data objects in main memory based on cache size. A cache size of a computer cache memory is determined, and a first data block is placed within a main computer memory. The first data block includes a first sub-block that will be frequently referenced. In addition, the first sub-block ends at a first ending address. A second data block is then placed within the main computer memory. The second data block includes a second sub-block that will be frequently referenced, and is placed such that the second sub-block will be contiguous with the first sub-block in the computer cache memory during execution.

Abstract: Clocked charge recycling differential logic circuits are activated by a delayed clock. According to the invention, when clocked charge recycling differential logic circuits of the invention are cascaded together, a delayed clock is provided for each clocked charge recycling differential logic circuit and each delayed clock is timed to at least the delay of the previous clocked charge recycling differential logic circuit. Consequently, according to the invention, a delay time is introduced to ensure each clocked charge recycling differential logic circuit of the invention is switched or “fired” only after it has received an input from the previous clocked charge recycling differential logic circuit stage. According to the invention, this is achieved without the use of complicated control circuitry.

Abstract: A method and apparatus for performing single-instruction bit field extraction and for counting a number of leading zeros in a sequence of bits on a general purpose processor are provided. The fast bit extraction operations are accomplished by executing a first instruction for extracting an arbitrary number of bits of a sequence of bits stored in two or more source registers of the processor starting at an arbitrary offset and the storing the extracted bits in a destination register. Both the source and the destination registers are specified by the instruction. In addition, a second instruction is provided for counting the number of leading zeros in a sequence of bits stored in two or more source registers of the processor and then storing a binary value representing the number of leading zeros in a destination register. Again the source and the destination registers are specified by the second instruction.

Abstract: An exclusive OR (XOR) circuit is provided to perform a logical XOR function on multiple bits that eliminates the XOR function hazard. The XOR circuit performs a logical XOR function on data values that have been encoded to prevent the XOR function hazard from occurring.

Abstract: Clocked charge recycling differential logic circuits are activated by a delayed clock. According to the invention, when clocked charge recycling differential logic circuits of the invention are cascaded together, a delayed clock is provided for each clocked charge recycling differential logic circuit and each delayed clock is timed to at least the delay of the previous clocked charge recycling differential logic circuit. Consequently, according to the invention, a delay time is introduced to ensure each clocked charge recycling differential logic circuit of the invention is switched or “fired” only after it has received an input from the previous clocked charge recycling differential logic circuit stage. According to the invention, this is achieved without the use of complicated control circuitry.

Abstract: A method for executing a process by a processing resource is provided. The method includes enabling the processing resource and advertising an availability of the processing resource to execute a job. Also included is receiving a request to execute the job on the processing resource. The method further includes launching a process service to execute the job, executing the job, and completing the execution of the job.

Abstract: A method for executing processing tasks in a distributed processing framework system is provided. The method includes identifying a main task of a tasklist and identifying a subtask of the main task. Also included is allocating computing resources for each of the main task and the subtask. The method further includes deploying the main task to a first computing system that is part of the distributed processing framework system. A code of the main task is executed on the first computing system. The code of the main task has program instructions for requesting loading of code for the subtask to a second computing system. The second computing system is part of the allocated computing resources. The code for the subtask is in client-server communication with the code for the main task, such that the code for the main task receives processing results directly from the code for the subtask.

Abstract: A method for managing an execution of a software processing job is provided. The method includes enabling a controller code and finding a suitable and available networked processing resource to execute the software processing job. The processing resource is configured to be registered with a registry service. Also included in the method is monitoring the execution of the software processing job by a selected processing resource as well as an availability of the selected processing resource while the controller code is enabled. The controller code is designed to be executed on a networked computer.

Abstract: A method for advertising an availability of a processing resource to execute a process is provided. The method includes enabling a registry service and the processing resource to register with the registry service. The processing resource is configured to be one of numbers of network interconnected resources. Also included in the method is enabling a system controller code to find and select a suitable and available processing resource registered with the registry service to execute the process. The system controller code is configured to be executed on a computer that is networked with the number of interconnected resources. The method further includes enabling the system controller code to communicate with a selected processing resource and updating a status of the processing resource in the registry service upon a termination of executing the process.

Abstract: The disclosed device is directed towards an air inlet bezel. The air inlet bezel comprises a body and a system air inlet grill contiguous with the body. A power supply air inlet grill is contiguous with the body and proximate to the system air inlet grill. A pair of ejector tabs is formed in the body. The ejector tabs are configured to manually couple the air inlet bezel to a power supply assembly.

Abstract: A method is provided, the method comprising associating each net of traces in a list of nets of the traces on a routed PCB with a parallelism index value and sorting the list of the nets of the traces on the routed PCB based on the parallelism index values. The method also comprises providing a list of victim nets of traces on the routed PCB based on the parallelism index values, each of the victim nets on the list of the victim nets associated with at least one offending net of traces on the routed PCB.

Abstract: An apparatus and method for actively reducing the temperature gradient of a substrate. The substrate is placed in thermal contact with a heat dissipation structure so as to dissipate heat from the substrate. Current is passed through a thermoelectric device, so as to provide cooling to at least one hot spot on the substrate.

Abstract: A method for significantly decreasing the number of times prior art coding schemes, such as variable length coding, are implemented in the course of encoding/decoding a given data block includes cataloging the occurrences, or locations, of a designated frequently occurring value in the data block and then excluding the frequently occurring value from the prior art coding scheme.

Abstract: A recovery logging method wherein when a node in a computer network becomes unavailable, file systems which require verification and are locked are logged in a recovery log and checking of other file systems continues. In this manner, the host node effectively utilizes time which would otherwise be spent waiting for a file system to become available. Upon completing available file system verifications, those file systems which were logged are checked for availability via background processing. When a logged file system becomes available, it is then verified. During the time spent waiting for a logged file system to become available, the affected node is available for other processing.

Abstract: A method for rendering a line segment extending in the positive-x direction and positive-y direction on a computer display given a starting point and an ending point, the starting point having the form (xs, ys) and the ending point having the form (xe, ye). In this method, &Dgr;x and &Dgr;y are computed using the formula &Dgr;x=|xe−xs| and &Dgr;y=|ye−ys|, respectively. Then dt(0)=(yf*&Dgr;x)−(xf*&Dgr;y) is computed, where xf is the fractional portion of xs and yf is the fractional portion of ys, which allows for more precision. If the line segment extends in the postive-x and positive-y directions, then for each column n containing a portion of said line segment the process: plots said current pixel if dt(n)<=0.5*&Dgr;x and plotting the pixel above said current pixel if dt(n)>0.5*&Dgr;x; moves said current pixel to the right one pixel if dt(n)<=0.5*&Dgr;x and moves said pixel to the right and up one pixel if dt(n)>0.

Abstract: In accordance with methods and systems consistent with the present invention, a number of improved network topologies are provided that have been selected to improve network performance based on various performance characteristics. The topologies are also selected to facilitate network reconfiguration, including adding nodes and removing, nodes. As a result, the network topologies in accordance with methods and systems consistent with the present invention do not follow a rigid, predefined pattern; rather, these topologies have been selected for network performance purposes as well as reconfiguration purposes.