Abstract: A synchronous dynamic random access memory controller has a high speed interface and a low speed interface. The high speed interface has a buffer with entries for receiving transactions, and the buffer has a valid bit for each entry. The entries store transactions that are received from a high speed bus. The low speed interface retrieves transactions from the buffer. The high speed interface and low speed interface each have state machines that synchronize the high speed and low speed interfaces using the valid bit for each of the entries.

Abstract: Operations including inserted prefetch operations that correspond to addressing chains may be scheduled above memory access operations that are likely-to-miss, thereby exploiting latency of the “martyred” likely-to-miss operations and improving execution performance of resulting code. More generally, certain pre-executable counterparts of likely-to-stall operations that form dependency chains may be scheduled above operations that are themselves likely-to-stall. Techniques have been developed to perform such scheduling. In particular, techniques have been developed that allow scheduled pre-executable operations (including prefetch operations and speculative loads) to be hoisted above intervening speculation boundaries. Speculative copies of dependency chains are employed in some realizations. Aggressive insertion of prefetch operations (including some used as markers) is employed in some realizations. Techniques for scheduling operations (e.g., in a compiler implementation) are described.

Abstract: A system and method includes a server that includes a processor and a memory system coupled that are coupled to a bus system. A network interface is coupled to the processor and an egress buffer is coupled to the processor and the network interface by an egress bus.

Abstract: A modular parser architecture and methods related thereto make use of a number of miniparsers. Each miniparser is capable of receiving input and generating an output dependent thereon. In one embodiment, a lexer or a miniparser capable of lexical analysis receives certain code and provides an abstract syntax tree. Each miniparser performs operations on a set of syntactical constructs to produce a corresponding output syntax tree, which in turn may become an input syntax tree for a next miniparser which may operate on a different set of syntactical constructs.

Abstract: Techniques have been developed whereby lock state sharing can be extended to provide a low-space overhead lock management facility with comprehensive support for bulk lock delegation. Operating in conjunction with delegation request validation methods, the techniques provide an efficient bulk lock delegation facility for many advanced transaction models. Some implementations in accordance with the present invention provide bulk lock delegation with computational costs that are generally independent of the number of locks being delegated. Accordingly, such implementations may be particularly attractive for systems that demand for fine-granularity locking, large transaction sizes (in term of number of locks acquired), and efficient delegation mechanisms.

Abstract: A lock management technique that combines low-space overhead via sharing of lock states of equal value with comprehensive support for bulk delegation of locks has been developed. Operating in conjunction with methods for validating delegation requests prior to their execution, bulk delegation of locks can be achieved with computational costs that are generally independent of the number of lock being delegated. This property, added to the low-space overhead representation of locks via lock state sharing, offer a combination that may be particularly attractive for systems that demand for fine-granularity locking, large transaction sizes (in term of number of locks acquired) and efficient bulk delegation mechanisms.

Abstract: A method and apparatus for thermally isolating a temperature sensor mounted on a printed circuit board from a heat generating component mounted on the printed circuit board is provided. Generally, a thermal isolation region, which may be comprised of a plurality of openings in the printed circuit board, is disposed about the temperature sensor to interrupt conductive transfer of heat from the heat generating component to the temperature sensor. The openings extend sufficiently far into the printed circuit board to remove at least a portion of a conductive layer, such as a power plane from the region surrounding the temperature sensor. Electrical power and signals may be provided to the temperature sensor through regions intermediate the openings.

Abstract: A system and method for providing hot swap capability with minimal changes in a system which uses existing circuitry and drivers. In one embodiment, a computer system has a host processor and a hot-swap-capable device, each coupled to a Compact PCI bus. The device includes one or more pre-existing circuits (ASICs and/or standard off-the-shelf circuits) and corresponding pre-existing drivers. A hot-swap-capable bus bridge is interposed between the circuits and the Compact PCI bus to provide hot swap functionality while allowing the pre-existing circuits and drivers to be used without modification. In one embodiment, an Intel 21554 is used as the hot-swap-capable bus bridge. The 21554 is programmed to emulate a transparent bridge. Modified drivers in the OBP firmware and OS software allow the system to recognize the 21554 in this transparent configuration and to probe the secondary side of the 21554 for the circuits.

Abstract: A method and apparatus for post-fabrication adjustment of a delay locked loop leakage current is provided. The adjustment system includes an adjustment circuit that adjusts a leakage current offset circuit to compensate for the leakage current of a capacitor in the delay locked loop. The capacitor connects to a control voltage of the delay locked loop. Such control of the leakage current in the delay locked loop allows a designer to achieve a desired delay locked loop operating characteristic after the delay locked loop has been fabricated.

Abstract: A system and method for storing error correction check words in computer memory modules. Check bits stored in physically adjacent locations within a dynamic random access memory (DRAM) chip are assigned to different check words. By assigning check bits to check words in this manner, multi-bit soft errors resulting from errors in two or more check bits stored in physically adjacent memory locations will appear as single-bit errors to an error correction subsystem. Similarly, the likelihood of multi-bit errors occurring in the same check word may be reduced.

Abstract: A heuristic algorithm which identifies loads guaranteed to hit the processor cache which further provides a “minimal” set of prefetches which are scheduled/inserted during compilation of a program is disclosed. The heuristic algorithm of the present invention utilizes the concept of a “cache line” (i.e., the data chunks received during memory operations) in conjunction with the concept of “related” memory operations for determining which prefetches are unnecessary for related memory operations; thus, generating a minimal number of prefetches for related memory operations.

Abstract: An integrated circuit package comprising EMI containment features. The EMI containment features include a first EMI containment configuration and a second EMI containment configuration. The second EMI containment configuration is disposed around the first EMI containment configuration. The first and second EMI containment configurations include vias coupled to at least one ground plane of the integrated circuit package.

Abstract: A bifurcation circuit uses dynamic asP* protocol. to exchange data among three or more FIFOs. Each FIFO contains a plurality of places containing data and a plurality of paths that exchange data between neighboring places. The bifurcator circuit generally comprises a control FIFO, two subordinate FIFOs and a bifurcation path coupled to all three FIFOs. The bifurcator circuit further comprises a chain of data latches coupled to all three FIFOs at the bifurcation path. A data value carried in the control FIFO determines which of the subordinate FIFOs exchanges data with the control FIFO. Each place in the FIFOs contains a set reset flip-flop in which the state of each place is held by a single wire and stabilized by a keeper. A single transistor sets or resets the state of the place. The pulse that changes the state of the control flip-flops also makes the data latches momentarily transparent. The bifurcator circuit is generally capable of a branch or join operations.

Abstract: According to one embodiment, a memory is disclosed. The memory includes a differential sense amplifier that receives a data input and a complementary data input; and a switching mechanism, coupled to the amplifier, that switches the data input and the complementary data input to minimize a negative bias temperature instability (NBTI) effect on the amplifier.

Abstract: A technique to detect and correct single bit errors and to detect paired bit errors in a data block. Two bits of the data block are paired and transferred on the same data path in different cycles. Check bits are computed prior to transferring the data block. A syndrome bits vector is computed when the data block is received. The syndrome bits vector includes a number of syndrome bits that is identical to the number of check bits. A value of the syndrome bits vector is used to detect and correct single bit errors and to detect paired double bit errors that occur in the data block without using an extended check bit. If the syndrome bits vector contains all zero bits, the data block is accepted without modification. If the syndrome bits vector is identical to a predetermined special vector V, a paired double bit error has occurred and either an unrecoverable error message is generated or a re-operation on the data block is requested.

Abstract: A method in a computer network having a first plurality of nodes coupled to a common network infrastructure and a distributed shared memory distributed among the first plurality of nodes for servicing a first memory access request by a first node of the computer network pertaining to a memory block having a home node different from the first node in the computer network. The computer network has no natural ordering mechanism and natural broadcast for servicing memory access requests from the plurality of nodes. The home node has no centralized directory for tracking states of the memory block in the plurality of nodes. The method includes the step of receiving via the common network infrastructure at the home node from the first node the first memory access request for the memory block.

Abstract: A plurality of clock signal phases are distributed to a circuit and at least one jitter source is coupled between at least two selected clock phases of the plurality of clock signal phases to introduce a jitter between at least the selected two clock signal phases. In a specific embodiment, the clock distribution system provides N clock phases and, if the phases have an order, there is one jitter source provided between each of the first N−1 phases and the following phase, so that each phase has a jitter relative to each other phase. Several implementations are possible for the jitter sources, which can be noise sources or pseudo-random noise sources, depending on which is easier to design and implement in a specific clock distribution system.

Abstract: By maintaining consistency of instruction or operation identification between code prepared for profiling and that prepared using profiling results, efficacy of profile-directed code optimizations can be improved. In particular, profile-directed optimizations based on stall statistics are facilitated in an environment in which correspondence maintained between (i) instructions or operations whose execution performance may be optimized (or which may provide an opportunity for optimization of other instructions or operations) and (ii) particular instructions or operations profiled.

Abstract: Program code executed in an environment in which latency exists between an execution event and detection of the execution event may be profiled using a technique that includes backtracking from a point in a representation of the program code, which coincides with the detection toward a preceding operation associated with the execution event. Backtracking identifies the preceding operation at a displacement from the detection point unless an ambiguity creating location is disposed between the detection point and the preceding operation. In general, the relevant set of ambiguity creating locations is processor implementation dependent and program code specific; however, branch targets locations, entry points, and trap or interrupt handler locations are common examples. In some realizations, the techniques may be used to associate cache miss (or hit) information with execution of particular memory access instructions.

Abstract: Instruction combining logic combines data from a plurality of write transactions before the data is written into main memory. In one embodiment, the instruction combining logic receives write transactions generated from store pair instructions, stores data from the write transactions in a buffer, and combines the data in the buffer. The combined data is subsequently written to memory in a single write transaction. The instruction combining logic may determine whether the data from the transactions are in the same cache line before combining them. A programmable timer may be used to measure the amount of time that has elapsed after the instruction combining logic receives the first write transaction. If the elapsed time exceeds a predetermined limit before another write instruction is received, the instruction combining logic combines the data in the buffer and writes it to memory in a single write transaction.