Abstract: A signal shielding technique that assigns voltage potential to shield wires based on the dominant switching direction of a signal is provided. The dominant switching direction is determined based on pre-charge based logic that drives the signal. By determining the voltage potential the signal is more likely to transition to, the shield wires can be implemented so that a discharge event occurs during the dominant transition. Because the signal is more likely to switch in the dominant switching direction, power supply collapses associated with charging events may be reduced.

Abstract: Various methods and systems for cooling high-density arrangements of disk drives are disclosed. A disk drive enclosure includes several stacked layers of disk drives and one or more air movers. Some of the air movers are configured to cool the disk drives by creating an airflow. The disk drives are configured to operate as a network or computer storage system. Instead of being arranged in a traditional, aligned arrangement, the disk drives are arranged in an offset or staggered arrangement so that at least one disk drive in a first layer is offset from an overlapping disk drive in a second layer. The offset is in a direction parallel to the plane that includes the first layer. As a result, at least part of one of the disk drives in the arrangement is exposed to more of the airflow than it would be exposed to in an aligned arrangement.

Abstract: In one embodiment, a processor is provided. The processor includes at least two cores, where each of the cores include a first level cache memory. Each of the cores are multi-threaded. In another embodiment, each of the cores includes four threads. In another embodiment a crossbar is included. A plurality of cache bank memories in communication with the at cores through the crossbar is provided. Each of the plurality of cache bank memories are in communication with a main memory interface. In another embodiment a buffer switch core in communication with each of the plurality of cache bank memories is also included. A server and a method for optimizing the utilization of a multithreaded processor core are also provided.

Abstract: In one embodiment of the present invention, a carrier plate assembly for use in an electrical system is disclosed, comprising a carrier plate capable of securing at least one system board. Each system board is capable of being inserted and removed from the carrier plate assembly without disturbing another system board connected to the carrier plate assembly. The carrier plate assembly is capable of releasable attachment to the electronic system and is capable of being inserted and removed from the electronic system without disturbing another assembly connected to the electronic system.

Abstract: Improved transposition of a matrix in a computer system may be accomplished while utilizing at most a single permutation vector. This greatly improves the speed and parallelability of the transpose operation. For a standard rectangular matrix having M rows and N columns and a size M×N, first n and q are determined, wherein N=n*q, and wherein M×q represents a block size and wherein N is evenly divisible by p. Then, the matrix is partitioned into n columns of size M×q. Then for each column n, elements are sequentially read within the column row-wise and sequentially written into a cache, then sequentially read from the cache and sequentially written row-wise back into the matrix in a memory in a column of size q×M. A permutation vector may then be applied to the matrix to arrive at the transpose. This method may be modified for special cases, such as square matrices, to further improve efficiency.

Abstract: Provided is a method of automatically generating data regarding errors in a software system. Contents of one or more files indicating errors in the software system are examined to determine software components responsible for the errors. The number of errors attributed to each of the software components responsible for the errors is determined. A size of the software component responsible for an error is also determined. In one embodiment, the size of the software components responsible of errors is correlated with the number of errors attributed to the software components.

Abstract: The present invention provides a method and apparatus for design verification. The method comprises operating a device in the system in a first state, modifying at least one operational characteristic of the device to operate in a second state, and determining if an error condition occurs in the system in response to modifying the operational characteristic of the device. The apparatus comprises an interface and a verification module adapted to receive a control signal from the interface and to adjust an operating characteristic of the apparatus to exercise a system in a manner that is capable of revealing one or more error conditions in the system in response to receiving the control signal.

Abstract: A distributed network search mechanism may be provided for consumers coupled to a network to search information providers coupled to the network. Consumers may make search requests according to a query routing protocol. A network hub may be configured to receive search requests from consumers. The hub may also receive registration requests from information providers according to the query routing protocol. Information providers register with the hub to indicate search queries in which they are interested in receiving. When a query request is received, the hub resolves the query request with a provider registration index. The hub matches search query information from the query request with provider registrations to determine which providers have registered to receive search queries like the current search query. The hub then routes the search query to matching providers according to the query routing protocol.

Abstract: A method and apparatus are provided for controlling delivery of electrical power to a hot swappable device. In a system that accepts hot swappable devices, a sensing circuit is provided to detect the hot swappable device being inserted into the system. The sensing circuit provides a signal indicative of the hot swappable device being inserted and a controller blocks delivery of system voltage to the hot swappable device for a preselected duration of time.

Abstract: One embodiment of the present invention provides a system that performs content screening on a message that is protected by end-to-end encryption. The system operates by receiving an encrypted message and an encrypted message key at a content screener from a firewall, the firewall having previously received the encrypted message and the encrypted message key from a source outside the firewall. The content screener decrypts the encrypted message key to restore the message key, and decrypts the encrypted message with the message key to restore the message. Next, the content screener screens the message to determine whether the message satisfies a screening criterion. If so, the system forwards the message to a destination within the firewall in a secure manner. In one embodiment of the present invention, the system decrypts the encrypted message key by sending the encrypted message key to the destination.

Abstract: Downloading code for communicating with a device that joins a network. When the device joins the network, it transmits a multicast packet including a reference to code for use in communicating with the device. Receivers in the network use the reference to download the code for constructing objects to communicate with the device, and the receivers respond with a reference to a lookup service in the network. Using the reference from the receivers, the device registers with the lookup service.

Abstract: A method and apparatus for dithering for color computer display systems includes the addition of a noise component to each of the color components of each pixel in a pseudo-random manner. The noise component is preferably different for each color component. Taking the image as a whole, the noise component repeats on a regular basis but is preferably selected so as not to repeat on adjacent pixels. The image is divided into squares of pixels and the same noise component is added to each of the same relative pixels from square to square. The preferred square of pixels is four pixels wide by four pixels high. The value of the noise component is chosen such that the most significant bit alternates both horizontally and vertically from pixel to pixel within the square of pixels.

Abstract: The present invention provides a memory array having an array structure that has at least one memory cell, including a word write bit line and a single transfer line. The memory array is also provided with a two-stage memory cell having a speculative storage node, a non-speculative storage node, and a circuit. The two-stage memory cell is electrically coupled to the array structure. Activation of the circuit causes a speculative data value stored in the speculative storage node to be written to the non-speculative storage node.

Abstract: A multi-thread computer system comprising an array of thread units and associated sets of execution units. The thread units are designed to be interconnected in a one-dimensional array with other thread units of the array via respective multi-bit bi-directional communication paths for transferring threads and for relaying activity values between thread units. Each thread unit has a thread control unit. Each thread control unit has on its left side a first multi-bit input and a first multi-bit output, each connected to a first one of the bi-directional communication paths, and on its right side a second multi-bit input and a second multi-bit output, each connected to a second one of the bi-directional communication paths.

Abstract: An integrated circuit device includes first and second arrays of semiconductor dice. Each array of dice is arranged in face-to-face relation to the other array of dice, thus forming a lower layer of dice and an upper layer of dice. The layers are aligned so that each upper layer die straddles two or more of the lower layer dice, thus defining overlap regions. In the overlap regions, signal pads of one layer are aligned with corresponding signal pads of the other layer. The two layers are spaced apart, thus creating a capacitance-based communication path between the upper and lower layers via the signal paths.

Abstract: A system for presenting hypermedia link information. A computer-implemented method for presenting hypermedia link information is described which relates to the user the characteristics of a data file pointed to by the hypermedia link. The computer system waits for an event to occur. This event is the user or system selecting one or more hypermedia links. The hypermedia link in this scenario points to a data file about which information is to be gathered. The computer system then requests information about the data file. In one embodiment, a cue is generated to communicate information about said data file to a user. This information may be conveyed to the user by auditory or visual means, such as a pop-up information box on the user's display. A powerful and convenient system for browsing hypermedia information is thus provided.

Abstract: A multiprocessor, multi-program, stop-the-world garbage collection program is described. The system initially over partitions the root sources, and then iteratively employs static and dynamic work balancing. Garbage collection threads compete dynamically for the initial partitions. Work stealing double-ended queues, where contention is reduced, are described to provide dynamic load balancing among the threads. Contention is resolved by using atomic instructions. The heap is broken into a young and an old generation where parallel semi-space copying is used to collect the young generation and parallel mark-compacting the old generation. Speed and efficiency of collection is enhanced by use of card tables and linking objects, and overflow conditions are efficiently handled by linking using class pointers. The garbage collection termination employs a global status word.

Abstract: A method and instruction set for geometry compression and decompression is disclosed. The method and instruction set includes one or more of the following attributes and instructions: a gosub-type instruction, a goto-type instruction, direct and indirect attribute-setting instructions, and matrix manipulation instructions. The instructions may be embedded within individual vertex descriptions, or they may be specified independent of any individual vertex in order to set global state information that applies to all vertices that follow the instruction. Individual vertex instructions may temporarily override the global settings. A graphics system configured to execute the instruction set is also disclosed.