Abstract: A phase locked loop design that uses a switch operatively connected to a loop filter capacitor to control a leakage current of the loop filter capacitor is provided. By positioning a switch in series with the loop filter capacitor, the leakage current of the loop filter capacitor may be controlled by switching the switch ‘on’ when a charge pump of the phase locked loop is ‘on’ and switching the switch ‘off’ when the charge pump is ‘off,’ thereby cumulatively reducing the leakage current of the loop filter capacitor throughput the operation of the phase locked loop. Control and reduction of the loop filter capacitor leakage current leads to more reliable and stable phase locked loop behavior.

Abstract: A scannable latch for use within a circuit path of a series of one or more dynamic circuits is provided. The scannable latch provides both latch functionality during normal operation and scan test functionality during scan mode operation. Particularly, the scannable latch has a dynamic input stage and a shadow latch, where the dynamic input stage's primary function occurs during normal operations and where the shadow latch's primary function occurs during scan operations. The scannable latch also has an output gate operatively connected to the dynamic input stage and shadow latch.

Abstract: A multiprocessing computer system provides the hardware support to properly test an I/O board while the system is running user application programs and while preventing a faulty board from causing a system crash. The system includes a centerplane that mounts multiple expander boards. Each expander board in turn connects a microprocessor board and an I/O board to the centerplane. Prior to testing, the replacement I/O board becomes a part of a dynamic system domain software partition after it has been inserted into an expander board of the multiprocessing computer system. Testing an I/O board involves executing a process using a microprocessor and memory on a microprocessor board to perform hardware tests on the I/O board. An error cage, address transaction cage, and interrupt transaction cage isolate any errors generated while the I/O board is being tested.

Abstract: A method and mechanism for arbitrating access to a bus. A client which is parked on a bus is allowed to gain access to the bus without having to go through arbitration. A client which is parked on the bus does not request access to the bus before beginning a transaction. If another client makes a high priority request for the bus, it gains access to the bus over a parked client. The parked client keeps a count of detected high priority request cycles. Upon reaching a threshold, the parked client requests the bus. The high priority client may then be made aware of the parked client's need for the bus and yield at an appropriate time.

Abstract: The present invention provides a method and apparatus for determining the trust worthiness of executable packets, e.g., internet applets, being transmitted within a computer network. The computer network includes both secured computers and unsecured computers, which are associated with secured nodes and unsecured nodes, respectively. Each executable packet has a source address and a destination address. In one embodiment, an intelligent firewall determines within a first degree of certainty whether the source address of an executable packet arriving at one of the secured computers is associated with anyone of the secured nodes, and also determines within a second degree of certainty whether the destination address of the executable packet is associated with anyone of the secured nodes.

Abstract: A method and apparatus for performing logic operations using a current mode logic circuit is provided. Further, a method and apparatus for performing high fan-in logic operations is provided. Further, a logic circuit that selectively steers current based upon a plurality of inputs is provided. Further, a method for performing logic operations using current steering is provided.

Abstract: A method and apparatus for post-fabrication adjustment of a delay locked loop leakage current is provided. The adjustment system includes a programmable current source that adjusts a leakage current offset circuit to compensate for the leakage current of a capacitor. The capacitor connects to a control voltage of the delay locked loop. The programmable current source includes at least one current source and switch to adjust the leakage current offset circuit. The programmable current source is selectively adjusted by a combinational logic circuit. Such control of the leakage current in the delay locked loop allows a designer to achieve a desired delay locked loop operating characteristic after fabrication of the adjustable delay locked loop.

Abstract: Methods, systems, and articles of manufacture consistent with the present invention improve display systems by providing a non-intrusive user interface where an application displays data in a designated area of a display screen that otherwise hides the data from view. The designated area contains at least one control element that, when selectively triggered, invokes a particular operation.

Abstract: A query object generator tool which generates interface definitions and code that implement a query object also generates a database schema access query object that retrieves the schema of an underlying database. Instead of retrieving data from the database, the database schema access query object retrieves “metadata”, including the names of tables and stored procedures in the database and their descriptions, from the database. The metadata is then displayed as part of a graphic user interface which is used to construct the SQL query implemented by the query object. In accordance with one embodiment of the invention, the database schema access object also verifies that an SQL query generated by a user is valid by submitting the query to the database engine of the underlying database. In accordance with another embodiment of the invention the database schema access object contains methods which perform automatic mapping of “standard” SQL data types to vendor-specific data.

Abstract: A method and apparatus for post-fabrication adjustment of a phase locked loop leakage current is provided. The adjustment system includes an adjustment circuit that adjusts a leakage current offset circuit to compensate for the leakage current of a capacitor in the phase locked loop. The capacitor connects to a control voltage of the phase locked loop. Such control of the leakage current in the phase locked loop allows a designer to achieve a desired phase locked loop operating characteristic after the phase locked loop has been fabricated.

Abstract: A system and method for determining the desired decoupling capacitors for power distribution systems having frequency dependent target impedance. In one embodiment, the target impedance may be a function of frequency, and thus may vary in value over a frequency range from 0 Hz to a corner frequency. A specific quantity of decoupling capacitors may be selected to provide decoupling for the power distribution for a given frequency within the frequency range. A total impedance provided by the specific quantity of selected decoupling capacitors may be calculated and compared to the calculated target impedance for the given frequency. If the total impedance provided by the specific quantity of selected decoupling capacitors is greater than the target impedance for the given frequency, the impedance may be adjusted by changing the quantity of capacitors. Capacitors may continue to be added until the total impedance is less than the target impedance.

Abstract: A system and method for rapid processing of scene-graph-based data and/or programs is disclosed. In one embodiment, the system may be configured to utilize a scene graph directly. In another embodiment, the system may be configured to generate a plurality of structures and thread that manage the data originally received as part of the scene graph. The structures and threads may be configured to convey information about state changes through the use of messaging. The system may include support for messaging between threads, messaging with time and/or event stamps, epochs to ensure consistency, and ancillary structures such as render-bins, geometry structures, and rendering environment structures.

Abstract: A method and apparatus for post-fabrication adjustment of a phased locked loop leakage current is provided. The adjustment system includes a programmable current source that adjusts a leakage current offset circuit to compensate for the leakage current of a capacitor. The capacitor connects to a control voltage of the phase locked loop. The programmable current source includes at least one current source and switch to adjust the leakage current offset circuit. The programmable current source is selectively adjusted by a combinational logic circuit. Such control of the leakage current in the phased locked loop allows a designer to achieve a desired phase locked loop operating characteristic after fabrication of the adjustable phase locked loop.

Abstract: A method for negotiating access to a private network for a mobile node that has migrated beyond the private network. A plurality of tunnel segments are composed with these tunnel segments composing a chain of a registration request from the mobile node to the private network.

Abstract: The present invention provides a method and apparatus for associating capabilities between a virtual input device and a display object. According to one embodiment of the present invention, capabilities are associated with a virtual input device by selecting a new capability, the new capability represented on a display device as a new capability display object, and associating the new capability with the virtual input device. According to another aspect of the invention, the virtual input device represents a user. Additionally, a display object can generate a private capability object for association with a virtual input device.

Abstract: In one embodiment, a server is provided. The server includes multiple application processor chips. Each of the multiple application processor chips includes multiple processing cores. Multiple memories corresponding to the multiple processor chips are included. The multiple memories are configured such that one processor chip is associated with one memory. A plurality of fabric chips enabling each of the multiple application processor chips to access any of the multiple memories are included. The data associated with one of the multiple application processor chips is stored across each of the multiple memories. In one embodiment, the application processor chips include a remote direct memory access (RDMA) and striping engine. The RDMA and striping engine is configured to store data in a striped manner across the multiple memories. A method for allowing multiple processors to exchange information through horizontal scaling is also provided.

Abstract: A multiprocessing computer system employs local and global address spaces and multiple access modes. A portion of the global memory of the multiprocessing computer system is allocated to each node, called local memory space. Two logical address spaces are mapped to the local memory of each node. A coherent memory replication (CMR) address space stores shadow pages of data from remote nodes and a local address space stores local data. A bit within a local physical address identifies whether data is a shadow page, which is stored in CMR space, or local data, which is stored in local address space. When a transaction requiring a coherency operation is performed, the CMR bit indicates whether a local physical address to global address translation is required. In one embodiment if the CMR bit is clear, the local physical address is the same as the global address and the local physical address is used for the coherency operation.

Abstract: An invention is provided for managing memory that includes a heap memory and scoped memory. The scoped memory is managed separately from the heap memory, and includes defining a scope tree structure having a root node and a plurality of child nodes. The child nodes are capable of having respective child nodes, however each child node has only one parent node. Each child node corresponds to a scoped memory space that forms a logical memory pool corresponding to a particular scoped memory. During memory management, a thread is allowed to enter a particular child node only through the parent node of the particular child node. In this manner, a thread executing in a particular scooped memory space allocates memory from the scoped memory corresponding to the particular scoped memory space.

Abstract: A system and method for isolating the execution of a plurality of applications. The applications may utilize or share one or more “original” classes. Only one copy of each original class is maintained, regardless of how many applications utilize it. Static fields are extracted from the original classes. A separate copy of the static fields is created for each of the utilizing applications. A static field class which includes instance fields corresponding to the static fields may be created, wherein each instance of the static field class corresponds to one of the utilizing applications. Access methods for the one or more static fields may be created, wherein the access methods are operable to access the corresponding separate copy of the static fields based upon the identity of the utilizing application.