Abstract: A base object class is defined for conversion between Java and XML. The base object class may include a first method for converting from Java to XML. The base object class may also include a second method for converting from XML to Java. Object classes may then be defined that extend the base object class and that facilitate conversion between Java and XML.

Abstract: A method moves data between processes in a computer-based system. Each process calls for one or more symbols in a first library. A second library comprises one or more equivalent symbols with Fast Sockets technology having a door interprocess communication mechanism. The call for a symbol in the first library from each process is intercepted and redirected to a corresponding symbol in the second library.

Abstract: The techniques of the present invention relate to allocating resources and managing multiple services and multiple users in a multiprocessing computer system. A virtual machine executive is booted on a computer system typically with multiple processors and multiple memory blocks. The virtual machine executive creates multiple virtual machines associated with multiple operating systems. A virtual machine executive provides the illusion that each virtual machine has its own dedicated hardware. The virtual machine executive either behaves as a file server, or hosts an operating system instance that behaves as a file server. System administration of the collection of operating system instances can be achieved by administering the operating system instance that behaves as a file server, rather than by administering each operating system instance alone.

Abstract: A probabilistic queue lock divides requesters for a lock into at least three sets. In one embodiment, the requesters are divided into the owner of the lock, the first waiting contender, and the other waiting contenders. The first waiting contender is made probabilistically more likely to obtain the lock by having it spin faster than the other waiting contenders. Because the other waiting contenders spin more slowly, the first waiting contender is more likely to be able to observe the free lock and acquire it before the other waiting contenders notice that it is free. The first of the other waiting contenders that determines that the previous first waiting contender has acquired the lock is promoted to be the new first waiting contender and begins spinning fast. Because only the first waiting contender is spinning fast on the lock, it is probable that only the first waiting contender will attempt to acquire the lock when it becomes available.

Abstract: A method and apparatus are provided for implementing Quality of Service (QoS) in a network environment in which client connections are maintained for limited periods of time. According to one embodiment, packet forwarding devices of a network, such as routers, bridges, and Local Area Network (LAN) switches, are caused to forward packets associated with a client according to a particular class of service, e.g., best-efforts, premium service, associated with the user of the client by assigning a network address, e.g., an Internet Protocol (IP) address, to the client based upon the particular class of service. According to another embodiment, a method of configuring the packet forwarding devices in a network is provided. For each class of service supported, information identifying one or more ranges of network addresses that are to receive a particular measure of service associated with the class of service is communicated to the packet forwarding devices.

Abstract: A boundary scan cell design which places the multiplexor before the functional flip-flip on the functional line path, reducing the multiplexor delay in the critical path. This optimizes the multiplexor and functional flip-flop orientation, allowing for a significant reduction in the time required from output of the functional flip-flop to a pin or to the interior of the CPU (the clock to q delay). In order to ensure that boundary scan mode functions properly, the functional flip-flop may be designed to act as a buffer, i.e. become transparent, when the boundary scan cell is in boundary scan mode.

Abstract: A database system wherein one or more entry databases store a plurality of entries. Each entry is of a given type that defines the fields of the entry. Each field contains or identifies an object with associated attributes or data. The type of each entry may further define behavior in the form of methods the entry can implement. An entry type which is a subtype of another inherits all fields and behavior of its super-type, and contains additional fields and/or defines new/modified behavior. Entries may be expressed in a Java™ programming language. The database system may further employ a search engine which allows queries to be made upon entries in the database. In one implementation, the queries include a read operation, a take operation, and a notify operation. Each query request includes a command indicating the type of operation, and a template which is an entry object having some or all of its fields set to specific values that must be matched exactly.

Abstract: A computer graphics system may comprise a graphics processor, a sample buffer, and a sample-to-pixel calculation unit. The graphics processor renders samples into the sample buffer in response to received graphics data. The sample-to-pixel calculation unit generates a plurality of output pixels by filtering the rendered samples based on a filter function. The pixels may be computed by generating a weighted sum of sample values (e.g. red sample values) for samples falling within the filter support. The coefficients used in the weighted sum may be added to form a normalization factor. One weighted sum of sample values may be computed per pixel attribute such as red, green, blue and alpha. The normalization factor may be computed in parallel with one or more of the weighted sums. Normalized pixel values may be obtained by dividing the weighted-sums by the normalization factor.

Abstract: A system and method are provided for efficient handling of streaming-data in a cache memory system (105) having a cache with several cache-lines (160) capable of storing data. In one aspect, a method is provided for determining before storing data to a cache-line if the storing of data will replace earlier data already stored in cache (135). If the storing of data will replace data in the cache (135), it is determined if the data that will be replaced is streaming-data. If the data to be replaced is not streaming-data, it is stored into victim cache (155). However, if the data to be replaced is streaming-data, it is not stored into the victim cache, thereby improving system efficiency by eliminating the copying of data to be replaced and avoiding replacing other earlier data in victim cache (155) that may be needed in the future.

Abstract: A fully integrated computer rack mount system comprising: at least one shelving unit configured to store computers; at least one electrical panel coupled to at least one of the at least one shelving unit, the at least one electrical panel configured to receive power from an external source; at least one network panel, coupled to at least one of the at least one shelving units, the at least one network panel configured to receive network connectivity from an outside source; a raceway apparatus coupled to the back plane or the front-plane of each of the at least one shelving unit, the raceway apparatus comprising a horizontal raceway and a vertical member, said vertical member comprising a power interface and a network interface; where said raceway apparatus is configured to allow each computer stored in the shelving units to be proximately connectable to the power interface and network interface; where the at least one electrical panel is coupled via said horizontal raceway to each power interface; and where t

Abstract: A method and apparatus for switching between threads of a program in response to a long-latency event. In one embodiment, the long-latency events are load or store operations which trigger a thread switch if there is a miss in the level 2 cache. In addition to providing separate groups of registers for multiple threads, a group of program address registers pointing to different threads are provided. A switching mechanism switches between the program address registers in response to the long-latency events.

Abstract: The disclosed system is directed towards a universal support system. The universal support system comprises a pair of arched bases and an arched beam coupled to the pair of arched bases. The universal support system also includes a multi-hinge rotatably coupled to the arched beam and a mounting bracket rotatably coupled to the multi-hinge, wherein the mounting bracket conforms with a mounting bracket standard for mounting displays.

Abstract: A symmetrical multiprocessing system includes a plurality of nodes interconnected by a hierarchical bus. To allow for the transfer of data between nodes and to restrict the global transfer of local transactions, a plurality of address partitions are defined: global space, local space, remote read space, and remote read and write space. Process private and local data is accessed using local space. Global data is accessed using global space. In one embodiment, a kernel of the operating system is resident in the local space of each node. Because the memory space where the kernel resides is designated as local space, no other nodes can write to, or corrupt, the node's kernel.

Abstract: A system that restricts the damaging effects of software faults that interact with test and configuration circuitry. This test and configuration circuitry includes a scan chain in the form of a serial linkage between memory elements within a circuit, thereby allowing a test input to be serially shifted into the memory elements. The system operates by receiving a test disable signal at the circuit. In response to the test disable signal, the system moves the circuit into a test disable mode, which limits any damaging effects to the circuit caused by shifting the test input into the memory elements in the scan chain. Next, the system shifts the test input into the memory elements in the scan chain. T he system also determines whether the test input will cause damage to the circuit after the test input is completely shifted into the scan chain. If so, the system holds the circuit in the test disable mode so that the test input cannot damage the circuit.

Abstract: A 180 degree bump placement layout for an integrated circuit power grid is provided. This layout improves integrated circuit performance and reliability and gives an integrated circuit designer added flexibility and uniformity in designing the integrated circuit. Further, a patterned bump array for a top metal layer of an integrated circuit having a plurality of 180 degree bump placement structures is provided.

Abstract: A method and apparatus for efficient and reliable multicasting in a network environment. In embodiments of the invention, a sender transmits identical information encapsulated in data packets to a plurality of receivers. Periodically, receivers submit responses that include control information regarding the loss or receipt of data packets transmitted by the sender. Using these information a sender retransmits any undelivered packets to intended receivers. Responses submitted by the participating receivers, generate a traffic flow that can consume a substantial portion of the network bandwidth. Thus, in embodiments of the invention, the rate at which the responses are submitted is monitored and controlled to minimize control traffic. Over congestion of the network bandwidth with control information is undesirable as it adversely effects the data transmission rate. Thus, in embodiments of the invention, packet loss responses are generated at time intervals.

Abstract: An improved mechanism for efficiently polling file descriptors in a large scale computer system is disclosed. The polling of the file descriptors is performed by first determining, based upon a set of indication information, which file descriptors are eligible for polling. A file descriptor is eligible for polling if the indication information for that file descriptor indicates that the file associated with that file descriptor might (but does not necessarily) have an event pending. Only if a file descriptor is determined to be eligible will the file descriptor and the file associated with the file descriptor be polled. By polling only the eligible file descriptors in a system, the overhead associated with the polling operation is kept to a minimum. As a result, even in a large scale system with a large number of file descriptors, polling is still performed efficiently.

Abstract: A method of designing an integrated circuit calculates the current density in each metal lead. The method can calculates a mean time to failure for at least one metal lead. The method can assume the metal leads are arranged in series only. The method can calculate the reliability of the integrated circuit. The method can arrange the set of metal leads by reliability. The method can divide the set of metal leads into at least two subsets, a subset requiring redesign and a subset meeting the reliability criteria. An embodiment includes an integrated circuit designed by the method taught. An embodiment includes a computer program product according to the method taught. An embodiment includes an integrated circuit including an integrated circuit designed according to the computer program product.

Abstract: Various embodiments of systems and methods for implementing filter-based attribute value access control are disclosed. In one embodiment, a method involves designating a location in the directory server, providing attribute related data that includes a filter expression, and selectively controlling access to an entry situated at the designated location using the filter expression in the attribute related data. For example, access to an attribute of the entry may be denied if a criterion defined by the filter expression associated with the attribute is not met by a first value of the attribute.

Abstract: A configuration manager federated bean is provided for each host computer in the three-tiered management system. The configuration manager federated bean for a host computer is contacted by federated beans that manage each of the data services when a data service starts and stops using a data storage volume associated with the host computer. The configuration manager bean maintains persistent configuration information for each data service. In one embodiment, configuration manager beans can operate in a clustered environment where several beans store configuration information in a single storage area. Each of the beans implements an arbitration protocol so that only one bean writes to the storage area at any given time.