Abstract: A computer system contains a small computer standard interface (SCSI) having a plurality of components to interface a plurality of external peripheral devices to the computer system in accordance with a SCSI specification. Within the computer system, the SCSI interface contains a SCSI bus having an internal SCSI terminator at an internal end of the SCSI bus, and an internal switchable SCSI terminator at an external end of the SCSI bus. The SCSI bus permits expansion beyond the computer system enclosure at the external side of the SCSI bus via an external connector and cable to interface external SCSI peripheral devices to the computer system. The internal switchable SCSI terminator senses whether any external SCSI external peripheral devices or an external terminator are attached to the SCSI bus. If external SCSI peripheral devices and/or an external terminator are attached to the SCSI bus, then the internal switchable SCSI terminator does not terminate the SCSI bus on the external side.

Abstract: A current crowding reduction technique involving the uniform displacement of vias around a bump is provided. By uniformly arranging vias around the bump on an integrated circuit, current can uniformly flow to and from the bump, effectively leading to reduced current density around the bump. Further, a method for reducing current crowding around a bump using an uniform arrangement of vias around the bump is provided.

Abstract: In accordance with methods and systems consistent with the present invention, an improved deadlock-free routing system is provided to a family of network topologies where both the configuration of the networks and the routings are designed to optimize performance. In this system, each network utilizes static routing tables that perform deadlock-free routing in an optimized manner to reduce the amount of communication overhead when routing traffic. Specifically, the routings in accordance with methods and systems consistent with the present invention require no more than two hops for networks up to a size of 16 nodes. As a result, the deadlock-free routing provided in accordance with methods and systems consistent with the present invention incurs less communications overhead than some conventional systems while still avoiding deadlock.

Abstract: A boundary scan cell design which places the multiplexor before the functional flip-flip on the functional line path, reducing the multiplexor delay in the critical path. This optimizes the multiplexor and functional flip-flop orientation, allowing for a significant reduction in the time required from output of the functional flip-flop to a pin or to the interior of the CPU (the clock to q delay). In order to ensure that boundary scan mode functions properly, the functional flip-flop may be designed to act as a buffer, i.e. become transparent, when the boundary scan cell is in boundary scan mode.

Abstract: A software method and apparatus for inserting prefetch operations according to data flow analysis. The invention traverses program code to ascertain memory operations and associated address forming operations, and calculates the relative distance between the two operations. If the distance between the two operations is such that a prefetch operation, inserted between the two operations and, in particular to one embodiment, immediately after the address forming operation, would increase the speed of the program when executed, then the prefetch operation is inserted.

Abstract: In embodiments of the invention, a method and apparatus for dynamic proxy insertion in network traffic path is described. According to one or more embodiments of the invention, a request and/or response message may be modified to include one or more thru-proxy tags to identify a network (or traffic) node (e.g., a proxy, server, or intermediary). For example, a request directed to a server or a response directed to a client may be altered to insert a plurality of intermediate or final destination designations. In so doing, a path of a request or response may be altered dynamically. A thru-proxy tag in a response may be inserted in a related request to identify a destination or node such that the request is sent to the destination in the thru-proxy tag before being sent to an origin server. Thru-proxy tags may be used to identify multiple and/or alternate destinations.

Abstract: A system and method providing address broadcast synchronization using multiple switches. The system for concurrently providing addresses to a plurality of devices includes a first switch and a second switch. The first switch is coupled to receive address requests from a first plurality of sources. The first switch is configured to output the address request from the first plurality of sources. The second switch is coupled to receive address requests from a second plurality of sources. The second switch is configured to receive the address request from the first plurality of sources from the first switch. The second switch is further configured to delay the address request from the second plurality of sources prior to arbitrating between ones of the address request from the second plurality of sources and ones of the address request from the first party of sources received from the first switch.

Abstract: A database system wherein one or more entry databases store a plurality of entries. Each entry is of a given type that defines the fields of the entry. Each field contains or identifies an object with associated attributes or data. The type of each entry may further define behavior in the form of methods the entry can implement. An entry type which is a subtype of another inherits all fields and behavior of its super-type, and contains additional fields and/or defines new/modified behavior. Entries may be expressed in a Java™ programming language. The database system may further employ a search engine which allows queries to be made upon entries in the database. In one implementation, the queries include a read operation, a take operation, and a notify operation. Each query request includes a command indicating the type of operation, and a template which is an entry object having some or all of its fields set to specific values that must be matched exactly.

Abstract: An integrated on-chip process, temperature, and voltage sensor is provided. Further, a method to monitor a process corner, temperature, and voltage on a computer chip is provided. Further, an on-chip voltage monitor is provided. Further, a method to monitor a voltage on a section of a computer chip is provided. Further, an integrated testing module having voltage, temperature, and sensor components is provided.

Abstract: Provided is a method, system, and program for configuring multiple resources in a system. A plurality of elements are provided that are capable of configuring resources in the system, wherein each element specifies configuration parameters to use to configure instances of the resource. Each resource is capable of being configured by multiple elements that provide a different configuration of the resource. Service information is maintained indicating at least one performance and availability attribute of the configuration of the resource by the element. At least one administrator specified performance and availability attribute for a configuration is received. A determination is made of at least one element for each resource having service information indicating at least one performance and availability attribute that satisfies the at least one administrator specified performance and availability attribute.

Abstract: In a RISC or CISC processor supporting the IEEE 754 Not-a-Number (NaN) standard and of the kind comprising a load/store unit, a register unit and an arithmetic logic unit, and wherein the load/store unit has an error flag for marking a datum loaded to the load/store unit following a load which has completed, but resulted in an error, the processor is provided with a bit pattern generator operatively arranged in an output path from the load/store unit to at least one of the register unit and the arithmetic logic unit so that a Not-a-Number value for the invalid datum is loaded into a destination one of the floating-point registers or the arithmetic logic unit. The arithmetic logic unit is configured to propagate the Not-a-Number value as a Quiet-Not-a-Number (QNaN) value through its operations. The QNaN value may be tested for in a datum by a system software command code provided for that purpose.

Abstract: A system and method for testing an integrated circuit is provided. The illustrative embodiment provides a scan cell for use with automatic test pattern generation (ATPG). In the scan cell of the illustrative embodiment, a flip-flop is configured as a master storage element and a latch is configured as a slave storage element. During standard operating mode, the flip-flop and the latch operate as standard storage elements in the circuit. During a test mode, the flip-flop and the latch form a shift register for shifting test pattern data through the circuit to identify and detect any faults in the circuit design.

Abstract: In accordance with methods and systems consistent with the present invention, a lease manager is provided for managing leases between clients and other network services. To use the lease manager, a client enters into a management lease with the lease manager, specifying an amount of time during which the lease manager can manage preexisting leases between the client and network services on behalf of the client. This management includes renewing the preexisting leases with the other network services. Further, the lease manager notifies the client when a lease between the lease manager and the client is near expiration. The lease manager also notifies the client of failed attempts to renew the preexisting leases, as well as the management lease, either with a network service or with the lease manager.

Abstract: A system and method for limiting power consumption of a computer memory system. The system and method includes selecting a memory access rate. The selected memory access rate corresponds to a desired average memory power consumption rate. A first time interval is started as a current time interval. A memory system is accessed. If the memory access rate has not been exceeded, then the access is applied to the memory system.

Abstract: A system and method for implementing an assertion check in an ATPG scan cell is provided. The assertion check includes an error signal generator within a scan cell that generates an error signal when there is a violation of necessary conditions for testing the integrated circuit using APTG. According to the illustrative embodiment, the scan cell comprises a set-reset flip-flop paired with a latch. The flip-flop is used as a master storage element and the latch is used as a slave storage element to form a scan path. The master flip-flop and the slave latch are connected to form a shift register for shifting test data through the circuit under test. A system clock drives the standard operational mode of the storage elements and a shift clock drives the test mode. An enable clock is used to activate the system clock and switch the scan cell between the standard operational mode and the test mode.

Abstract: A system for leasing a group membership in a distributed processing system is provided. In accordance with this system, a remote object requests from an activation group a membership in the activation group for a period of time. Responsive to this request, the activation group determines an appropriate lease period during which time the remote object becomes a member of the activation group and runs in the same address space as other objects of the activation group.

Abstract: A system and method for analyzing simultaneous switching noise. In one embodiment, a model may be provided for the electronic circuit to be analyzed. The electronic circuit may be an integrated circuit, a multi-chip module, a printed circuit assembly, or other type, and may in some embodiments include combinations of these types. The electronic circuit may include a plurality of drivers, each of which may be coupled to a power plane, a ground plane, and a transmission line. The connection of the driver may be accurately modeled in this manner. Each driver may be configured to switch between a logic high voltage and a logic low voltage. The modeled electronic circuit may also include a voltage source coupled to the power plane and the ground plane, a voltage regulator module, and a plurality of decoupling capacitors. The simultaneous switching of a plurality of drivers, from a logic high to a logic low, or vice versa, may be simulated.

Abstract: The disclosed system is directed towards a high storage volume support system. The high storage volume support system includes an arched beam having a first end and a second end and a first base coupled to the first end. The high storage volume support system includes a second base coupled to the second end and a storage volume formed by the arched beam, the first base and the second base.

Abstract: Cache line optimization involves computing where cache misses are in a control flow and assigning probabilities to cache misses. Cache lines may be scheduled based on the assigned probabilities and where the cache misses are in the control flow. Cache line probabilities may be calculated based on the relationship of the cache line and where the cache misses are in the control flow. A control flow may be pruned before calculating cache line probabilities. Function call sites may be used to prune the control flow. Address generation of a cache miss may be duplicated to speculatively hoist address generation and the associated prefetch. References may be selected for optimization, identifying cache lines, and mapping the selected references. Dependencies within the cache lines may be determined and the cache lines may be scheduled based on the determined dependencies and probabilities of usefulness.

Abstract: A network file system and method wherein a storage area network Universal File System allows any host in a heterogeneous based storage area network to read or write data as if in its native format. Any host coupled to the storage area network may be configured to access any storage device on the storage area network. By augmenting the operating system of a host, the host is enabled to mount the Universal File System. Subsequent to mounting the Universal File System, a host may read data from and write data to the Universal File System.