Abstract: “A system [comprises] includes a virtual private network and an external device interconnected by a digital network. The virtual private network has a firewall, at least one internal device and a nameserver each having a network address. The internal device also has a secondary address, and the nameserver is configured to provide an association between the secondary address and the network address. The firewall, in response to a request from the external device to establish a connection therebetween, provides the external device with the network address of the nameserver. The external device, in response to a request from an operator or the like, including the internal device's secondary address, requesting access to the internal device, generates a network address request message for transmission over the connection to the firewall requesting resolution of the network address associated with the secondary address.

Abstract: One embodiment of the present invention provides a system that facilitates prototyping asynchronous circuits. The system first receives a design of an asynchronous circuit, which includes asynchronous cells. The system maps the asynchronous cells of the asynchronous circuit onto clocked synchronous cells within a logic array or programmable logic array device such as standard-cell gate-arrays and field-programmable gate-arrays. The mapping delays the generation of the asynchronous clock events until the next clock event, thus preserving the full functionality of the asynchronous circuit. The system then implements the mapped circuit on the synchronous device to perform the functions that are mapped from the asynchronous circuit. Finally, the system operates the synchronous device, and the results of operating the synchronous device are used to verify the design of the asynchronous circuit.

Abstract: Embodiments of the invention comprise a method and apparatus for avoiding array class creation in, for example, virtual machines for object-oriented programming languages. Embodiments of the invention reduce the internal structures created for arrays at runtime, thereby reducing memory consumption. Unlike in a traditional implementation, where a separate array class is created for each array of different type, in an embodiment of the invention the type information is stored in array instances instead. Array classes are not created at all. Rather, the root class of the class hierarchy (e.g., “java.lang.Object”) is used as the class of each array instance. When an array instance is instantiated, a reference to the “java.lang.Object” class is created in the class field of the array instance and the type information is stored in the instance itself. In one embodiment of the invention, an integer type value is stored in a special type field of the array instance.

Abstract: Techniques for type checking in Java computing environments are disclosed. As will be appreciated, the techniques can be used by a Java virtual machine to efficiently perform type checking. In one embodiment, a Java class hierarchy is implemented in an internal class representation. The Java class hierarchy represents the hierarchical relationship of the parent classes for the Java class. The Java class hierarchy can be implemented, for example, as an array of class references. The array of class references can be used to efficiently perform type checking in Java computing environments. As a result, the performance of Java virtual machines, especially those operating with limited resources, can be significantly enhanced.

Abstract: Clocked half-rail differential logic circuits are activated by a delayed clock. According to the invention, when clocked half-rail differential logic circuits of the invention are cascaded together, a delayed clock is provided for each clocked half-rail differential logic circuit and each delayed clock is timed to at least the delay of the previous clocked half-rail differential logic circuit. Consequently, according to the invention, a delay time is introduced to ensure each clocked half-rail differential logic circuit of the invention is switched or “fired” only after it has received an input from the previous clocked half-rail differential logic circuit stage. According to the invention, this is achieved without the use of complicated control circuitry.

Abstract: Techniques for handling exceptions raised during the execution of Java computer programs are disclosed. The techniques can be used by a Java virtual machine to efficiently handle exceptions. A method descriptor is implemented in a Java method frame which is stored in the Java execution stack. The method descriptor provides one or more references to exception handlers associated with the Java method. The references can be used to quickly identify and invoke the appropriate exception handler. This can be achieved without having to use a native language execution stack. As a result, the overhead associated with several returns from native functions (routines or methods) can be avoided since the information needed to invoke the appropriate exception handler can be obtained efficiently from the Java execution stack. Accordingly, the performance of Java virtual machines, especially those operating with limited resources, can be significantly enhanced.

Abstract: A disk scheduling system with bounded request reordering. Disk access requests may be performed during traversals of a disk head across a disk. Each traversal may have a specified direction of motion. A plurality of disk accesses may be performed during a disk head traversal. The overall number of disk access requests for a given disk head traversal may be limited to a maximum number N. By limiting the number of disk requests for each traversal, a bound may effectively be placed on the amount of time it takes to satisfy any single disk request.

Abstract: Methods and systems for automated memory test modeling generation and validation are provided. Information supplied by a graphical user interface is used to generate a customized memory primitive. The memory primitive subsequently undergoes a two phase validation to test for correct functioning.

Abstract: Techniques for executing synchronized Java methods are disclosed. As such, the techniques can be implemented in a Java virtual machine to efficiently execute Java instructions. As will be appreciated, monitors (e.g., locks) associated with Java objects for which the synchronized method are being performed are accessed quickly. In other words, the monitors can be quickly released without having to repeat several time-consuming operations which have to be performed in conventional systems. This, in turn, reduces the number of operations that need to be performed to execute synchronized Java methods. As a result, the performance of virtual machines, especially those operating with limited resources, is improved.

Abstract: Provided is a method, system, and program for maintaining a database of data objects. A first data object implemented in a first programming language including attributes and attribute values for a class is received. The first data object is transformed to a second data object implemented in a second programming language, wherein the second data object includes the attributes and attribute values of the class included in the first data object. The second data object is added to the database, wherein the database is capable of storing multiple data objects implemented in the second programming language.

Abstract: Provided is a computer implemented method, system, and program for discovering a topology of a switch from an initiator device. The switch includes a plurality of switch ports. A plurality of Input/Output (I/O) devices are connected to the switch ports, wherein each I/O device and the initiator device connect to the switch through one of the switch ports. The initiator and I/O devices communicate on a first network configured by the switch and the initiator device communicates with the switch over a second network. The initiator device performs submitting a first query over the first network to the switch requesting a unique address of a plurality of I/O devices that are accessible to the initiator device over the first network. In response to the first query to the switch on the first network, the unique address of each I/O device is received from the switch. A second query is submitted over the second network to the switch for information on switch ports on the switch.

Abstract: A method includes adding direction to interference edges of a register interference graph and choosing a node of the register interference graph to spill based upon a pass degree of the node. By using the pass degree, the node that caused the greatest interference with allocation of the variables to the physical registers is preferentially chosen to be spilled.

Abstract: A local computer stores a current program such as an operating system or an application. A network server stores a latest program which is a latest version of the current program, and an identifier program for generating an identification corresponding to the latest program upon interrogation. An updater program is alternatively stored on the local computer or the network server for causing the latest program to be transferred from the network server to the local computer and replace the current computer program. The current program and the latest program each include a startup program configured to interrogate the identifier program, determine if the identification corresponds to the current program, and if the identification does not correspond to the current program, run the updater program.

Abstract: One embodiment of the present invention provides a system for generating a pseudo-random non-periodic digital sequence. The system operates by receiving a non-periodic signal at a data input of a flip-flop. This non-periodic signal is sampled at the flip-flop with a clock signal, thereby producing the pseudo-random non-periodic digital sequence at the output of the flip-flop.

Abstract: A single-chip central processing unit (CPU) includes a processing core and a complete cache-coherent I/O system that operates asynchronously with the processing core. An internal communications protocol uses synchronizers and data buffers to transfer information between a clock domain of the processing core and a clock domain of the I/O system. The synchronizers transfer control and handshake signal between clock domains, but the data buffer transfers data without input or output synchronization circuitry for data bits. Throughput for the system is high because the processing unit has direct access to I/O system so that no delays are incurred for complex mechanisms which are commonly employed between a CPU and an external I/O chip-set. Throughput is further increased by holding data from one DMA transfer in the data buffer for use in a subsequent DMA transfer.

Abstract: Methods and apparatus for efficiently enabling an alternate return address associated with a function call to essentially be stored such that the alternate return address may be readily accessed are disclosed. According to one aspect of the present invention, a method for enabling a return address associated with a function called by a routine to be efficiently stored includes calling the function from within the routine while the routine is executing. In general, the function is external to the routine. The function, once called, begins executing. Eventually, the function returns to the routine. Specifically, the function returns to a location in the routine that is identified by an expected return point, or normal return address. The instruction in the routine that corresponds to the expected return point is a dummy instruction that executes with a low computational overhead but does not affect program execution.

Abstract: A virtual printer for print jobs printed on networked printers. First, the virtual printer checks a user's preferences regarding a print job the user wishes to send such as speed and image quality. Next, the virtual printer determines, using a server, database or other query, the most appropriate printer complying with the print job preferences, and located physically near the user and sends the print job to that printer. If the printer returns an error signal, the virtual printer will determine a different printer which closely complies with the print job preferences and re-send the print job. If a busy signal is returned, the user will be given the choice of waiting or having the virtual printer automatically determine the next available appropriate printer. When the print job is complete, the user will be notified of the physical location of the printer where the print job was processed.

Abstract: A transmission gate immune to noise that selectively delivers/draws charge to/from a noisy input node in order to ensure that an output node is not adversely affected by the noise on the input node is provided. Further, an NMOS pass gate immune to noise that delivers charge to a noisy input node in order to ensure that an output node is not adversely affected by the noise on the input node is provided. Further, a PMOS pass gate immune to noise that draws charge from a noisy input node in order to ensure that an output node is not adversely affected by the noise on the input node is provided.

Abstract: A method for programming a controller of a memory unit has been developed. The method includes inputting variable initialization parameters of the memory unit and a clock delay and a command delay for each parameter. Based on each pair of clock delays and command delays, calculate a set of delays for a read command and a write command. Calculate the system performance for each pair of clock and command delays bases on the read and write delays and select the initial parameters that offer optimum system performance.

Abstract: A client is given control over the pre-fetching of resources. The client may be, for example, resident on an electronic device such as a computer system that caches resources. The resources may be, for instance, web pages. Identifying property values that are intrinsically tied to the contents of the resources are used to determine whether resources are already resident within the cache prior to pre-fetching the resources. In addition, the client may request information regarding a resource to assist the client in determining whether to pre-fetch the resource. Such information may include the size of the resource and other information.