Abstract: Disclosed is a low threshold asymmetric MOS device having a pocket region with a graded concentration profile. The pocket region includes a relatively high dopant atom concentration (of the same conductivity type as the bulk region) abutting either the device's source or its drain along the side of the source or drain that faces the device's channel region. The pocket region's graded concentration profile provides a lower dopant concentration near the substrate surface and an increasing dopant concentration below that surface. This provides a relatively low resistance conduction path through the pocket region, while allowing the device's threshold voltage to be somewhat higher at the pocket region. The asymmetric device can also include a counter dopant region located beneath its substrate surface. This forces current to flow in the substrate but just above the region of high counter dopant concentration, where the resistance is relatively low.

Abstract: In an out-of-order processor having single-precision floating-point registers aliased into double-precision floating-point registers, a single-precision floating-point arithmetic operation having four possible register dependencies is converted into two microinstructions which are processed normally within the processor. The first microinstruction is coded to perform the arithmetic operation specified by the single-precision instruction using the first and second source registers specified and storing the result in a phantom register. The second microinstruction is coded for merging the contents of the phantom register and the destination register specified. Each microinstruction has at most two possible register dependencies, thereby reducing the total number of register dependencies which the processor is required to track.

Abstract: A method and apparatus for system building with a transactional interpreter. Unlike interpreters of the prior art, a transactional interpreter permits large interpreter-based operations, such as a system build, to resume processing from a point within the operation, i.e., the most recently completed transaction, rather than restarting from the beginning when the operation is interrupted. Control over transaction processing is maintained at the virtual machine level by the interpreter, and is therefore transparent with respect to the user of the interpreting software. In one embodiment of the invention, a virtual machine comprises a computer system running a transactional interpreter process with an underlying database such as an object-oriented database. The transactional interpreter individually processes instructions from an input stack, and, between the processing of each instruction, determines whether a commit operation is to be performed, marking the end of a transaction.

Abstract: The pin count of a processor is substantially reduced while effectively maintaining processor performance by using a staging register to receive and store a first data segment from a bus. A second data segment is received from the bus in a subsequent bus cycle and loaded into a cache. A steering circuit dynamically selects the transfer of the first or the second segment to a processor core, and orders positioning of the first and second data segments into the cache. In some embodiments, the cache is a first level cache and a second level cache is inserted between the bus and the processor. In these embodiments, the processor includes a bypassing circuit for designating the ordering of bus data in response to a memory access that misses the first level cache and hits the second level cache.

Abstract: A data processing system comprises a plurality of nodes and a serial data bus interconnecting the nodes in series in a closed loop, for passing address and data information. At least one processing node includes a processor, a printed circuit board and a memory which is partitioned into a plurality of sections, including a first section for directly sharable memory located on the printed circuit board, and a second section for block sharable memory. A local bus connects the processor, block sharable memory and printed circuit board, for transferring data in parallel from the processor to the directly sharable memory on the printed circuit board, and for transferring data from the block sharable memory to the printed circuit board.

Abstract: A circuit for accelerating digital signal transitions includes an input/output node to receive a digital input signal. A transition termination circuit is connected to the input/output node to generate a transition termination signal when the digital input signal approaches a final signal level. A transition acceleration circuit is connected to the input/output node and the transition termination circuit. The transition acceleration circuit is activated to accelerate the digital input signal to a full digital signal level when the digital input signal achieves an initial signal transition level and is deactivated when the transition termination signal is received.

Abstract: A method and apparatus for generating additional implicit keys from a key [K.sub.ij ].sub.N without the necessity of generating a new Diffie-Helman (DH) certificate or requiring communication between nodes to change implicit master keys is disclosed. A first data processing device (node I) is coupled to a private network which is in turn coupled to the Internet. A second data processing device (node J) is coupled to the same, or to a different network, which is also coupled to the Internet, such that node I communicates with node J using the Internet protocol. Node I is provided with a secret value i and a public value. Data packets (referred to as "datagrams") are encrypted to enhance network security. Each node maintains an internal value of N which is incremented based on time and upon the receipt of a data packet from another node. The key [K.sub.ij ].sub.N.sbsb.i is derived from the appropriate quantity of .varies..sup.Nij by using high order key-sized bits of the respective quantity.

Abstract: The present invention includes methods for caching method frames using multiple stack cache management units to provide access to multiple portions of the method frames. In some embodiments of the invention, a first frame component of a first method frame is cached in a first stack cache management unit. A second frame component of the first method frame is cached in a second stack cache management unit. In addition, a first frame component of a second method frame is also cached in the second stack cache management unit and a second frame component of the second method frame is cached in the first stack cache management unit. The first frame components of the method frames can be, for example, operand stacks of the method frames. The second frame components of the method frames can be, for example, the arguments and local variable areas of the method frames.

Abstract: The invention is a system that provides programmable clock delays for logic circuits. The system makes use of the boundary-scan register chain incorporated into logic devices for testing purposes. In the invention, delay code values are loaded through the boundary-scan register chain into delay code registers. The delay codes are then used to program the value of delay elements in the logic circuit. An evaluation logic circuit can be included to compare the output data with an expected test pattern and thereby verify the acceptability of the delay values. The invention thereby allows delays to be adjusted to correct functionality and/or optimize circuit performance without requiring modifications to the circuit design.

Abstract: A trigger is provided in association with a network naming service, such as DNS (Domain Name Service), that handles client requests for an application. The trigger comprises a set of executable instructions referenced by a resource record associated with an identifier of the application. In response to a client request concerning the application, the resource record is retrieved and the instructions are executed. In one implementation of a trigger, a DNS server provides load balancing among a plurality of servers within a network name space (e.g., domain or sub-domain) offering an application program (or replicated service) that is known by a virtual server name. A policy is selected for choosing a preferred server from the plurality of servers according to a specified status or operational characteristic of the application instances, such as the least-loaded instance of the application or the instance with the fastest response time.

Abstract: Method and circuitry for implementing low voltage input buffers using low voltage CMOS transistors are disclosed. Various novel circuit techniques enable the input buffer to safely receive and reliably detect input logic signals in the presence of overshoot or undershoot conditions. In a preferred embodiment, the source terminals of input transistors are biased such that the impact of overshooting or undershooting signals at the input terminal are drastically reduced.

Abstract: A system for executing a software application comprising a plurality of hardware independent bytecodes is provided comprising a computing system that generates bytecodes, a virtual machine, remote to the computing system, that receives a plurality of bytecodes from said computing system, and executes said plurality of bytecodes, a system for testing said bytecodes against a set of predetermined criteria in which the testing is securely distributed between said virtual machine and said computing system so that the bytecode verification completed by the computing system is authenticated by the virtual machine prior to the execution of the bytecodes by said virtual machine. A method for distributed bytecode verification is also provided.

Abstract: A method and apparatus for timely delivery of classes and objects is provided. A header comprising timing information is attached to said classes and/or objects. A "start loading" time and a "load by" time are specified in the header. Other classes and/or objects to be loaded are also specified in the header. Optional compression, security, and/or error resilience schemes are also specified in the header. A process for creating the header and attaching it to a class or object is provided. A process for receiving and processing a class or object with an attached header is provided. Embodiments of the invention allow timely delivery of classes and/or objects over a wide variety of transport mechanisms, including unreliable transport mechanisms and those lacking any guarantees of timely delivery.

Abstract: To compensate for process, activity and temperature-induced device threshold variations in a semiconductor circuit having a transistor, a potential of the gate the transistor is held to a preset subthreshold potential, and a channel current of the channel region is compared with a reference current to obtain a comparison result. A bias potential of a substrate is adjusted according to the comparison result to hold the subthreshold current at the reference current.

Abstract: A method and apparatus for transferring data between devices on a bus is described, the apparatus comprising a producer device having an output, and a first data management device having an input and a bus interface. An the output of the producer device is coupled to an input of the data management device. An output of the data management device is coupled to the bus. The preferred method of the present invention includes the steps of causing the data management device to receive data packets from the producer device in single address-data phases, grouping at least two data packets destined for consecutive memory addresses, reorganizing the data within the first-in, first-out memory so that the at least two data packets destined for consecutive memory addresses are consecutive in the first-in, first-out memory, and transferring the data group over the bus using a single arbitration phase, a single address phase,. and a number of data phases corresponding to the number of data phases in said group.

Abstract: In a client/server computing system, a method and apparatus for efficiently storing entries in a log file during disconnected client operations. An encoder utilizes a log file and a write file table for logging the write operations performed by the client during disconnected operations. The logging method employed by the encoding module logs in the log file only writes associated for different files. The encoding module tracks the status of the entries in the log file with a write file table containing the most recent sequence number associated with a file entry of the log file. Upon reconnection of the client to the server, a decoding module replays the events in the correct chronological order by transferring the file data modified during the period of disconnection in the order dictated by the write file table. A deferred write list is accessed by the decoding module for temporary storage any write operations whose replay should be delayed to preserve the relative order of events.

Abstract: Methods, apparatus, and computer program products for linking stack messages to information relevant to stack entries and for generating the stack messages by adding link information to the stack messages. The stack messages are displayed to the user without the link information. Portions of the visible stack messages pertaining to the link information are highlighted, and upon selection by the user of the highlighted portion of the stack message, information relevant to the highlighted stack message is automatically displayed, for example, by running an editor, loading the source file corresponding to the message, and displaying the relevant portion of a source file.

Abstract: A fault-tolerant computer architecture is described wherein the effect of hardware faults is diminished. The architecture employs a main data bus having a plurality of interface slots for interconnecting conventional computer sub-systems. The number and type of sub-systems may vary considerably, however, a central processor sub-system which encompasses the inventive elements of the invention is always included. The central processor sub-system employs a plurality of central processing modules operating in parallel in a substantially synchronized manner. One of the central processing modules operates as a master central processing module, and is the only module capable of reading data from and writing data to the main data bus. The master central processing module is initially chosen arbitrarily from among the central processing modules.

Abstract: A microprocessor capable of performing multimedia and non-multimedia operations provided a plurality of stack based instructions is provided. The microprocessor includes a stack processor coupled to a stack capable of storing values, a register processor coupled to a register file capable of storing values, and a copy-unit having a first port coupled to the stack and a second port coupled to the register file being configured to copy data between the register file and the stack. The microprocessor also includes logic coupled to receive the plurality of stack based instructions from memory, cache, or other storage devices coupled to the microprocessor. The logic is configured to determine which of the plurality of stack based instructions are regular stack instructions and which of the plurality of stack based instructions are extended stack instructions.

Abstract: Three-dimensional compressed geometry is decompressed with a unit having an input FIFO receiving compressed data bits and outputting to an input block state machine and an input block, whose outputs are coupled to a barrel shifter unit. Input block output also is input to Huffman tables that output to the state machine. The state machine output also is coupled to a data path controller whose output is coupled to a tag decoder, and to a normal processor receiving output from the barrel shifter unit. The decompressor unit also includes a position/color processor that receives output from the barrel shifter unit. Outputs from the normal processor and position/color processor are multiplexed to a format converter. For instructions in the data stream that generate output to the format converter, the decompression unit generates a tag sent to the tag decoder in parallel with bits for normals that are sent to the format converter.