Abstract: An integrated processor includes a microprocessor core and a bus interface unit. The integrated processor receives a reference clock signal and an external clock signal. The frequency of the reference clock signal is compared to the frequency of the external clock signal. Based upon this comparison, the appropriate frequency for the internal clock signal that controls the bus interface unit is determined. A clock generation circuit, such as a phase-locked loop, generates the appropriate frequency for the internal clock signal based upon the comparison of the reference clock signal and external clock signal.

Abstract: A method for controlling a gating circuit of an electronic system incorporating a scan architecture complying with IEEE Standard 1149.1 such that the gating circuit applies mutually exclusive signals to, for example, a decoded multiplexer. The gating circuit receives input signals from flip-flops that are part of a scan chain, is selectively controllable by a control signal to transmit predetermined mutually exclusive signals to the select inputs of the multiplexer during a scan mode. Alternatively, the gating circuit is controllable by the control signal to pass the input signals to the multiplexer in a normal operation or test mode. A mutual exclusivity circuit is provided to generate the control signal. During the scan mode, the control signal is generated at a first logic level such that the gating circuit transmits the predetermined mutually exclusive signals to the multiplexer while test values are being scanned into the flip-flops.

Abstract: An interconnect controller for use in an arbitrary topology collection of nodes in a network suitable for use for both data sharing and distributed computing. The interconnect controller provides four (4) serial ports and two (2) parallel ports for communicating with adjacent nodes in a network. Linked ports between two nodes provide a continuous stream of information with idle packets filling non-data transfer cases. The logic of the interconnect controller provides for adaptive routing and to topology independence and allows for the sharing of a common clock for synchronizing the packet transmission.

Abstract: A thermal conducting material for providing lateral thermal conduction across a surface of an integrated circuit and for enhancing thermal dissipation from the integrated circuit. The integrated circuit is incorporated within a semiconductor device having a cavity package. A layer of the thermal conducting material, preferably electrically non-conductive, is disposed on a surface of an integrated circuit in the form of a die to provide lateral heat conduction to reduce the number of hot spots within the integrated circuit. Alternatively, the thermal conducting, electrically non-conductive material may be used to fill a cavity within the cavity package so that the cavity package dissipates heat in a more effective manner.

Abstract: An interconnect structure includes in a first layer a clock line and a ground line running substantially parallel to the clock line, and a plurality of conductive regions lying in a second layer parallel to the first layer. The ground line is coupled to a source of ground potential. The conductive regions are aligned with the clock line and are disposed around a signal line routed in the second layer across the clock line. The conductive regions are electrically connected to the ground line, thereby forming a shield for the clock line that helps prevent clock signals propagated on the clock line from electromagnetically coupling with other signal lines. In one embodiment, a clock distribution network includes conductive regions (501, 503, 505 . . . ) in the metal layer below the clock line layer and two parallel ground lines (201, 203) in the same metal layer as the clock line (101). The conductive regions (501, 503, 505 . . .

Abstract: A data cache unit associated with a processor, the data cache unit including a multi-ported non-blocking cache receiving a data access request from a lower level device in the processor. A memory scheduling window includes at least one row of entries, wherein each entry includes an address field holding an address of the access request. A conflict map field within at least some of the entries is coupled to a conflict checking unit. The conflict checking unit responds to the address fields by setting bits in the conflict map fields to indicate intra-row conflicts between entries. A picker coupled to the memory scheduling window responds to the conflict map fields so as to identify groups of non-conflicting entries to launch in parallel at the multi-ported non-blocking cache.

Abstract: A multi-layer network element for forwarding received packets from an input port to one or more output ports. The packet is examined to look for different types of forwarding information. An associative memory is searched once for each type of information. The results from the two searches are combined to forward the packet to the appropriate one or more output ports. The packet may be examined for other information as well to make the forwarding decisions. In one embodiment, the invention examines the packet for layer 2 information as the first type and layer 3, and perhaps some layer 4, information as the second type. The results are merged to determine the most appropriate combination of layer 2 or layer 3 forwarding decisions for the packet.

Abstract: A method and apparatus that allows a Web page designer to specify tooltips for his Web page. Tooltips are text areas that display automatically when the user places the cursor over predetermined text on a display device. The invention also enables Web browser software to display the tooltips specified by the designer. The HTML format extension allows a Web page designer to specify the text over which the user must place the cursor to activate tooltips. The HTML extension also allows the designer to specify the tooltip text that will be displayed when the cursor reaches the specified text. Using the present invention, the designer only needs to specify tooltips for any given information once per page, even though the displayed information may appear multiple times on the Web page.

Abstract: A unified array access for two logically different arrays is provided. The first array includes CAM cells arranged in n rows and x columns. At least one CAM cell is coupled to a match line, a CAM word line, and to a CAM bit line. The second array includes first RAM cells arranged in n rows and y columns and second RAM cells arranged in n rows and z columns. At least one first RAM cell is coupled to a RAM word line, and to a first RAM bit line. At least one second RAM cell is coupled to the same RAM word line, and a second RAM bit line. RAM word line drivers are provided to activate the first and second RAM cells during a read or write access thereof. At least one RAM word driver has an output coupled to first and second RAM cells. N match sense amplifiers are provided, at least one of which has an input coupled to one of the CAM cells via a match line, and an output coupled to at least one RAM word driver.

Abstract: An electronic circuit verification system and method includes an HDL circuit simulator and a circuit simulation verifier that pass control back and forth between each other, and that cooperate so as to perform circuit verification tasks than would be very difficult to perform using only the HDL circuit simulator. The circuit simulation verifier executes a test bench so as to define operational correctness and/or performance criteria, including at least one Expect Event, each Expect Event comprising a combination of one or more signal values that are expected to occur during simulation, and a time frame during which the signal value combination is expected to occur. The circuit simulation verifier includes instructions for blocking execution of a thread of execution associated with the test bench until the earlier of the combination of one or more signal values occurring during simulation and the time frame expiring.

Abstract: Method for increasing data-processing speed in computer systems containing at least one microprocessor, a memory device, and a so-called cache connected to the processor, in which the cache is arranged to fetch data from the addresses in the memory device requested by the processor and then also fetches data from one or several addresses in the memory device not requested by the processor. The computer system includes a circuit called the stream-detection circuit, connected to interact with a cache such that the stream-detection circuit detects the addresses which the processor requests in the cache and registers whether the addresses requested already existed in cache. The stream-detection circuit is arranged such that it is made to detect one or several sequential series of addresses requested by the processor in the cache.

Abstract: Apparatus, methods, and computer program products are disclosed for improving the performance of subsequent compilations of a source program. The initial compilation of the source program journals computationally expensive intermediate compilation data. Subsequent compilations, instead of recomputing this data, uses the intermediate compilation data from the journal. Thus the compiler has improved performance during subsequent compilations of the source program. One aspect of the invention applies to dynamic compilers to reduce the startup delay caused by compiling the source program when the program is invoked.

Abstract: Data is collected from multiple data packets for group transfer on a data path so as to maximize utilization of the data path. A particularly suitable data path is one that is coupled to transfer data to a graphics frame buffer. In collecting data from multiple data packets, data from individual packets are designated for loading onto the data path. In specific embodiments, data from a packet will be designated for loading onto the data path only if it is determined that the data is noncacheable data, the data would not overwrite other valid designated but not yet loaded data, or the resulting data to be transferred as a group would target data locations within a permissible locus of data locations, such as a contiguous range of addresses. The designated data are loaded onto the data path as a group for actual transfer. In a specific embodiment, there is a mask associated with each data packet that indicates which portions of each packet's possible data actually contain data to be transferred.

Abstract: User messages are automatically positioned on a display at a location at which a user's gaze is directed as indicated by an eyetracker. When a user has read the message, as indicated by his eyes having traversed the text, the message is automatically cleared. The message may also be cleared by a user's spoken response.

Abstract: A computer system includes a bus interface with a plurality of data buffers. Each data buffer is clocked by an individual clock signal. To reduce the power consumption of the bus interface unit, the clock signals of the data buffers that are inactive are disabled during the period of inactivity. The bus interface unit includes a clock control unit that monitors a data bus coupled to the bus interface to determine when a bus cycle begins and the type of bus cycle. The clock control unit additionally monitors memory and CPU buffer signals that indicate which, if any, buffers are being accessed by the memory or CPU. From this information, the clock control unit determines which buffers are active and inactive, and outputs control signals to a clock unit to disable the clock signals associated with inactive buffers.

Abstract: The present invention pertains to a system and method for simulating multiple clusters of independent computer nodes in a single machine. A cluster contains one or more computer nodes interconnected by a communications link. A user can simulate a cluster of n nodes by generating n user-level procedures where each user-level procedure represents the kernel of a respective node. An additional mechanism is provided which allows a user to exercise the operation of any intended function in any of the nodes in any of the clusters.

Abstract: The present invention provides a verifier for use in conjunction with programs utilizing data type specific bytecodes for verifying the proper operation of the executable program prior to actual execution by a host processor. A verifier is provided which includes a virtual stack for temporarily storing stack information which parallels the typical stack operations required during the execution a bytecode program. The verifier also includes a stack snapshot storage structure having a snapshot directory and stack snapshot storage area for storing the state of the virtual stack at various points during program verification so as to assure proper stack manipulations by the source program. A two step source program verification process is provided for in which the source program is initially loaded into the verifier and a first pass source program evaluation is performed.

Abstract: A non-inclusive cache system includes an external cache and a plurality of on-chip caches each having a set of tags associated therewith, with at least one of the on-chip caches including data which is absent from the external cache. A pipelined snoop bus is ported to each of the set of tags of the plurality of on-chip caches and transmits a snoop address to the plurality of on-chip caches. A system interface unit is responsive to a received snoop request to scan the external cache and to apply the snoop address of the snoop request to the pipelined snoop bus. A plurality of response signal lines respectively extend from the plurality of on-chip caches to the system interface unit, each of the signal lines for transmitting a snoop response from a corresponding one of the on-board caches to the system interface unit. The set of tags can be implemented by dual-porting the cache tags, or by providing a duplicate and dedicated set of snoop tags.

Abstract: A system, method, apparatus, and computer program product for avoiding aircraft collisions with stationary obstacles. The aircraft is provided with a simplified uncluttered onboard display of all objects which are in or proximate to the projected path of the aircraft at its particular altitude plus or minus a predetermined increment, such as 100 feet constituting a hazard zone. The display presents the hazards in that zone in geographical relationship to the position and path of the aircraft. In addition to the obstacles in the hazard zone the display may also present topographical features of the underlying terrain. This information is in the form of a muted presentation of a topographical moving map. As the aircraft approaches a hazard in the hazard zone the presentation of the obstacles or hazards within the zone is enhanced to draw increasing attention of the pilot.

Abstract: A system and a process for providing improved interfacing to a data source storing a plurality of data using query objects are described. The data source includes a schema describing organization of the data within the data source and an interface defined in a query language. A set of data manipulations are encapsulated in the query object and implemented in the query language. Each such encapsulated data manipulation conforms to the schema of the data source. A connection is handled via the interface between the query object and the data source. At least one such encapsulated data manipulation is performed on the data source in response to a request from a client. A resultant set of the data received in response to the at least one such data manipulation from the data source is processed. The resultant set of the data is provided as pre-determined data types to the client.