Abstract: A computer system includes a program executer that executes verifiable architecture neutral programs and a class loader that prohibits the loading and execution of non-verifiable programs unless (A) the non-verifiable program resides in a trusted repository of such programs, or (B) the non-verifiable program is indirectly verifiable by way of a digital signature on the non-verifiable program that proves the program was produced by a trusted source. In the preferred embodiment, verifiable architecture neutral programs are Java bytecode programs whose integrity is verified using a Java bytecode program verifier. The non-verifiable programs are generally architecture specific compiled programs generated with the assistance of a compiler. Each architecture specific program typically includes two signatures, including one by the compiling party and one by the compiler. Each digital signature includes a signing party identifier and an encrypted message.

Abstract: The present invention provides a memory system that caches method frames using multiple stack cache management units to provide access to multiple portions of the method frames. In some embodiments of the invention, a memory system includes a main memory circuit, a first stack cache management unit, and a second stack cache management unit. The first stack cache management unit is configured to cache a first frame component of a first method frame and a second frame component of a second method frame. The second stack cache management unit is configured to cache a second frame component of the first method frame and a first frame component of the second method frame. Some embodiments of the memory system also includes a main memory cache coupled between the main memory circuit and the stack cache management units. The first frame components of the method frames can be, for example, the operand stacks method frames.

Abstract: A distributed computer system has a program compiling computer and a program executing computer. The program compiling computer is operated by a compiling party and includes a compiler that, when the digital signature of the originating party of an architecture neutral program has been verified, (A) compiles the architecture neutral program code of the architecture neutral program into architecture specific program code in the architecture specific language identified by the compile to information in the architecture neutral program, and (B) appends to the architecture specific program code a digital signature of the compiling party to generate an architecture specific program.

Abstract: A high-performance band combine function to transform a source image of n bands to a destination image of m bands. A source image vector is multiplied with a transformation matrix having n+l columns and m rows. The values in the transformation matrix may be user-selected. The product of the source image and the transformation matrix is a destination image vector. The destination image vector may be displayed on a computer monitor. To perform the function in a digital system, the pixels of the source image are converted to a partitioned format. The source image is multiplied with the transformation matrix values using partitioned arithmetic. In the digital system, a plurality of partitioned arithmetic operations may be performed in parallel.

Abstract: A bracket having two parallel sides and an interconnecting crosspiece is attached to a disk drive or similar peripheral with the sides of the bracket extending longitudinally of the sides of the drive and the crosspiece extending across the front of the drive. A chassis of a computer or the like has internal parallel sides formed with horizontal guides to receive the bracket, a substantially open front face and an internal connector engageable with a mating connector on the rear of the drive when the bracket is fully inserted in the chassis. The sides of the bracket have features to protect the drive from horizontal and vertical vibrations. A handle is pivoted to the crosspiece near one end moveable between at least three positions: a first or latched position parallel to the crosspiece, a second position swinging out at about a 15.degree. angle and a third position at about a 45.degree. angle.

Abstract: A multimedia server system includes a disk array subsystem including a plurality of multimedia files, e.g., movies, a media file system manager for managing the storage of the plurality of multimedia files within the disk array subsystem, and a playlist which includes a list of titles of specific multimedia files to be played at designated times. The multimedia server system advantageously includes synchronization parameters associated with each of titles specified by the playlist. The synchronization parameters are programmed to specify the manner in which particular files should be truncated in order to compensate for admission delays. An admission delay synchronization unit receives the synchronization parameters and truncates the multimedia files as specified by the synchronization parameters. In one implementation, a first synchronization parameter is used to specify that the current file should be truncated at the time for the play of the next file.

Abstract: A computer system includes a central processing unit with an internal memory controller. The internal memory controller interacts with an external cache and a primary memory through a single unified memory bus. The internal memory controller generates a shared row address that is applied to the unified memory bus during an address fetching operation to simultaneously access a row in primary memory and an address in external cache. The internal memory controller may also generate a shared column address that is applied to the unified memory bus during a data return operation to simultaneously specify a column in primary memory and an address in external cache.

Abstract: A circuit which can compensate for process variations in controlling a drive transistor, whether for driving internal circuits or an output driver. A drive circuit is connected to the gate of the drive transistor, and is controlled by a control logic signal. In response to the control logic signal transitioning, the drive circuit will drive the gate to a voltage which is set depending upon the amount of process variation.

Abstract: A system for avoiding exceptional conditions during execution of a program comprises an execution enviornment for executing the program and a fix-up code generation subsystem. The program comprises an instruction stream comprising a series of instructions, and the execution environment includes an exceptional condition detector for detecting at least one predetermined type of exceptional condition in connection with execution of each instruction in the instruction stream. The fix-up code generation subsystem is responsive to detection by the execution environment of an exceptional condition of the predetermined type in connection with execution of an instruction in the instruction stream for generating fix-up code which, when processed, would avoid the exceptional condition of that predetermined type, and substitutes the fix-up code in the instruction stream for the instruction in the instruction stream for which the at least one exceptional condition was detected.

Abstract: Apparatus, methods, and computer program products are disclosed for reducing the overhead associated with performing area-image operations on a tiled image. The invention detects when an area-image operation, that uses a source pixel contribution map, requires pixel values from one or more adjacent tiles. The invention also generates a list of boxes that represent pixel image information. These boxes are split with respect to the image edges and the tile edges within the image. The split boxes are used to direct memory buffer allocation for cobbled portions of the image and to leave the majority of the tile's pixel information to be operated on within memory buffer holding the tile. Thus, the invention provides a mechanism to assemble image data that crosses tile edges without copying major portions of the tile from one memory buffer to another.

Abstract: An instruction accelerator which includes a processor and an associative memory. The processor is coupled to receive a stream of instructions and a corresponding stream of instruction identifier values. The instructions include at least one non-quick instruction which has a first associated data set which must be accessed prior to executing the non-quick instruction. A memory, which is coupled to the processor, stores one or more instruction identifier values and one or more associated data sets. The memory receives the stream of instruction identifier values. When a current instruction identifier value in the stream of instruction identifier values matches an instruction identifier value stored in the memory, an associated data set is accessed from the memory.

Abstract: A system for maintaining reliable packet distribution in a ring network with support for strongly ordered, nonidempotent commands. Each consumer node on the network maintains a record of the sequence of packets that have passed through that node, and the state of each of the packets at the time it passed through, including a record of the last known good packet and its sequence number. When a producer node detects an error condition in an acknowledgment for a packet, resends all packets beginning with the last known good packet. Each consumer node is able to process or reject the resent packets, including packets that may already have been processed, which it is aware of due to the packet and state records for all packets.

Abstract: An access control database defines access rights through the use of access control objects. The access control objects include group objects, each defining a group and a set of users who are members of the group, and rule objects. Some of the rule objects each specify a set of the group objects, a set of the management objects, and access rights by the users who are members of the groups defined by the specified set of the group objects to the specified set of management objects. A plurality of access control servers are used to process access requests. Each access control server controls access to a distinct subset of the management objects in accordance with the access rights specified in the access control database. At least one of the access control servers receives access requests from the users and distributes the received access requests among the access control servers for processing. A subset of the access requests specify operations to be performed on specified sets of the management objects.

Abstract: A counterflow pipeline is provided which includes an instruction pipeline having a plurality of stages for transmitting instruction packets in a first direction and a result pipeline having a plurality of stages for transmitting result packets in a second direction opposite the first direction. Each of the result pipeline stages corresponds to an instruction pipeline stage, the associated instruction and result pipeline stages being part of a counterflow pipeline stage. Arbitration logic coupled between the instruction and result pipelines facilitates the movement of instruction and result packets in the stages of the instruction pipeline and result pipeline, respectively, using a four-phase level signaling protocol. The arbitration logic prevents instruction and result packets from passing each other in their respective pipelines by inhibiting them from being simultaneously released from adjacent counterflow pipeline stages. Thus, any necessary interaction between the two data packets may take place.

Abstract: A system and method for indexing between video streams in an interactive video delivery system. The interactive video delivery system includes at least one media server which stores video streams having different presentation rates. In one embodiment, the system stores a normal play stream and one or more corresponding trick play streams. The trick play video streams are fast forward and/or fast reverse video streams. The system generates index tables or look-up tables between the normal play and trick play video streams which enable indexing between the streams, and uses these look-up tables to switch back and forth between the streams. In creating the index tables, the system first analyzes the normal play stream and creates a normal play time standard based on presentation timestamps from the normal play stream. The system then creates an index table or look-up table for each of the normal play and trick play video streams using the normal play time standard.

Abstract: A system for maintaining reliable packet distribution in a ring network with support for strongly ordered, nonidempotent commands. Each consumer node on the network maintains a record of the sequence of packets that have passed through that node, and the state of each of the packets at the time it passed through, including a record of the last known good packet and its sequence number. When a producer node detects an error condition in an acknowledgment for a packet, resends all packets beginning with the last known good packet. Each consumer node is able to process or reject the resent packets, including packets that may already have been processed, which it is aware of due to the packet and state records for all packets.

Abstract: A non-inclusive cache system includes an external cache and a plurality of on-chip caches each having a set of tags associated therewith, with at least one of the on-chip caches including data which is absent from the external cache. A pipelined snoop bus is ported to each of the set of tags of the plurality of on-chip caches and transmits a snoop address to the plurality of on-chip caches. A system interface unit is responsive to a received snoop request to scan the external cache and to apply the snoop address of the snoop request to the pipelined snoop bus. A plurality of response signal lines respectively extend from the plurality of on-chip caches to the system interface unit, each of the signal lines for transmitting a snoop response from a corresponding one of the on-board caches to the system interface unit. The set of tags can be implemented by dual-porting the cache tags, or by providing a duplicate and dedicated set of snoop tags.

Abstract: The present invention comprises a method for providing feedback to the user of a graphical user interface using visual and operational clues. In an embodiment of the invention, the user is provided visual clues that inform the user in what direction the display area can be scrolled. The display area may contain a list, a text box, a pop-up menu or any kind of data. Operational clues help the user determine what actions move the list and what actions do not move the list. The invention can be implemented in the form of a list. A list is comprised of one or more fields. At the top of the list and at the bottom of the list is a blank space that functions as one of the visual clues. The purpose of the blank space is to inform the user they are at the top of the list and cannot scroll any further up or that they are at the bottom of the list and cannot scroll any further down. Another form of visual clue is provided through the use of partially visible fields.