Abstract: A transmitter/receiver chip includes circuitry for testing the bit error rate of the chip. A controlled amount of noise is introduced to the chip to vary a timing parameter of a transmit clock, resulting in an increase in a bit error rate of the chip. Artificially increasing the bit error rate of the chip reduces the amount of time required to test the chip to determine the acceptability of the chip and its actual bit error rate.

Abstract: A first computer system (34) compiles a source program into machine code for a register-oriented microprocessor, optimizing the global allocation of microprocessor registers in the process. It then translates the resultant code into generic-machine operand-stack-oriented code. In performing the translation, it generates code that preserves the register-oriented code's microprocessor-register allocation by filling the operand stack from local variables chosen in accordance with a predetermined correspondence between local variables and microprocessor registers. That code also stores the operand stack's contents in accordance with that same correspondence. A second computer system (32), which employs the register-oriented microprocessor, converts the resultant generic machine code into its own machine code in accordance with the same association between local variables to microprocessor registers.

Abstract: A system and method for efficient implementation of a multi-port logic first-in, first-out ("FIFO") structure or particular utility in high clock speed integrated circuit ("IC") processor design which provides for reduced on-chip area requirements and fewer and less timing critical electrical interconnect paths. The advantageous reduction in IC area and enhanced performance disclosed herein is enabled through the rotation of the inputs and outputs of the FIFO; maintenance of decoded head and tail pointers, and folding the FIFO entry locations such that the entries are arranged in an interleaved fashion.

Abstract: To reduce threshold levels in fully depleted SOI devices having back gate wells, the channel regions of the devices are formed of an intrinsic or pseudo-intrinsic semiconductor. Also, multiple well structures or isolation regions are formed below the oxide layer to reduce diode junction leakage between the back gate wells of the devices.

Abstract: An apparatus and method for optimizing a non-inclusive hierarchical cache memory system that includes a first and second cache for storing information. The first and second cache are arranged in an hierarchical manner such as a level two and level three cache in a cache system having three levels of cache. The level two and level three cache hold information non-inclusively, while a dual directory holds tags and states that are duplicates of the tags and states held for the level two cache. All snoop requests (snoops) are passed to the dual directory by a snoop queue. The dual directory is used to determine whether a snoop request sent by snoop queue is relevant to the contents of level two cache, avoiding the need to send the snoop request to level two cache if there is a "miss" in the dual directory.

Abstract: An automated apparatus detects electromigration violations in an integrated circuit design. Starting from the lowest hierarchy of the design so far completed, the parasitic (resistance and capacitance) component values extracted from a layout file are propagated up. Then, at the top-most level, lumping algorithms are employed to calculate the parasitic values for all of the top-most level nets. These values are then passed back down to the lower levels and then at each level, the layout is checked using previously computed parasitic values and EM limits. A peak current, AC-average current and AC-rms current are calculated for every layout, and then compared with the process EM rules for violations, in which the optimum line width and number of vias are specified for each interconnection.

Abstract: The present invention provides a modular infrastructure for electronic commerce that allows electronic financial instruments to work with a variety of different protocols. One embodiment of the present invention receives a request for an operation, and checks compatibility between the operation and available protocols for the operation to determine a set of compatible protocols. Next, the system checks compatibility between the set of compatible protocols and available instruments for the operation to determine a set of compatible instruments. If the set of compatible instruments includes at least one instrument, the system selects a compatible instrument and a corresponding compatible protocol, and uses this instrument and protocol to perform the operation.

Abstract: In the present invention, a method for directing parallel processing computing device to perform the operation of setting a signed value of N bits to an absolute value comprises the steps of: performing an arithmetic shift right of N-1 bit to form a bit mask; performing an exclusive-OR logical operation with the signed value of N bits and the bit mask to form a result; and subtracting the bit mask from the result of the exclusive-OR logical operation to form the absolute value of the signed value of N bits. Further, an apparatus for parallel processing a signed value to form an absolute value comprises: means for performing an arithmetic shift right of N-1 bit to form a bit mask; means for performing an exclusive-OR logical operation with the signed value of N bits and the bit mask to form a result; and means for subtracting the bit mask from the result of the exclusive-OR logical operation to form the absolute value of the signed value of N bits.

Abstract: A computer system and method edits a hierarchical document that has starttags and endtags and leaf contents between ones of the starttags and endtags. The computer system includes a memory, a user interface, and a hierarchical document editor. The memory stores a data structure representing the hierarchical document. The data structure includes an array of items and a corresponding index and a corresponding index offset for each of the items. Each of the items represents a corresponding one of the starttags, endtags, and leaf contents. The user interface displays the hierarchical document. It also issues commands for editing the hierarchical document. The hierarchical document editor edits the hierarchical document in response to the issued commands by traversing ones of the items in the data structure based on the indexes and index offsets of the traversed ones of the items.

Abstract: A preferred embodiment of the present invention includes a method and apparatus for allocating and using IP addresses in a network of client systems. More specifically, the present invention includes a router which monitors the assignments of IP addresses by a DHCP server. As each IP address is assigned, the router associates the assigned IP address with an trusted identifier which identifies the client system. Subsequently, if the router received a packet directed at the assigned IP address, the router forwards the packet to the client system having an trusted identifier associated with the destination address of the IP packet. Additionally, if the router receives a packet from a client system, it uses the trusted identifier of the client system to find IP addresses associated with the client system. If the source address of the IP packet is not included in the IP addresses associated with the client system, the packet is discarded.

Abstract: An arbiter is disclosed for determining a sequence of signals indicative of events occurring variously on at least two input connections. The arbiter includes a first input connection and a second input connection for carrying the signals indicative of events. A first input queue for storing representations of events that are waiting to be processed is connected to the first input connection, and a second input queue also for storing representations of events that are waiting to be processed is connected to the second input connection.

Abstract: A circuit and method for segregating address entries of memory, internal to an address translation unit, into locked and unlocked regions. The locked region is a portion of the memory that can be invalidated by a lesser number of events than the unlocked region. In one embodiment, replacement circuitry of the address translation unit may invalidate address translations only stored in the unlocked region. The replacement circuitry comprises a counter to produce a first count value upon detecting that at least a first command has been issued to the address translation unit and each entry of the memory is currently in a valid state. Also, the replacement circuitry comprises an increment controller to control the counter to produce the first count value that addresses an entry of the memory within the second address range.

Abstract: An active digital voltage regulator circuit stores energy during times when the local power supply voltage is greater than a predefined voltage, e.g., during times when the parasitic inductances supplement the local power supply voltage. The active digital voltage regulator circuit uses the stored energy to supplement the local power supply voltage during times when the local power supply voltage starts to collapse, e.g., during periods when inductive losses are preventing the power supply from maintaining the local power supply voltage. A control circuit within the regulator circuit is a combination of two self-biasing and off-set nulling power supply monitor circuits. Each power supply monitor circuit further includes a differencing, non-overlapped, dual-output amplifier connected to the first and second power supply input lines.

Abstract: A method and apparatus for high availability and caching data storage devices. According to a preferred embodiment of the invention, there is provided an apparatus. The apparatus comprises a primary controller, a secondary controller having the same address as that of the primary controller, a switching circuit coupled to the primary and secondary controllers, and a control circuit coupled to the switching circuit. According to this preferred embodiment of the invention, in a normal operation, the control circuit sets the switching circuit so that the primary controller receives and responds to input data supplied from a host, and the secondary controller receives the input data. In a fail-over operation in which the primary controller fails, the control circuit sets the switching circuit so that the primary controller is disabled, and the secondary controller receives and responds to the input data supplied from the host. The fail-over is transparent to the host.

Abstract: The present invention includes a method and apparatus for registering devices in a computer network. Initially, for an unregistered device, the network establishes a unregistered enabled packet filter. The unregistered enabled packet filter discards all IP packets that originate at the unregistered device, except IP packets addressed to a registration server. IP packets sent to the registration server allow a user to authenticate the unregistered device. Subsequently, the network replaces the unregistered enabled packet filter with a registered enable packet filter. The registered enabled packet filter allows the device to send packets to a login server within the computer network. Subsequently, if the user fails to pay subscription fees (of for other applicable reason) the registered enabled packet filter may be replaced with a registered disabled packet filter to prevent the device from sending packets to the network.

Abstract: An input buffer circuit implemented with low voltage transistors, that is capable of receiving and recognizing input logic signals having higher voltage levels is disclosed. The present invention uses various circuit techniques to ensure that no transistor in the input buffer circuitry undergoes voltages higher than that allowed by the fabrication process, even though the input signal voltage may swing well beyond the tolerable voltage levels. This is accomplished without compromising the reliability of the input buffer circuit in detecting the logic levels of the input signal.

Abstract: In a preferred embodiment, the present invention provides a method and system for organizing selectable elements on a graphical user interface (GUI). Initially, the method provides at least two selectable elements for display on a GUI. Each selectable element is associated with a target element when it is selected. The method generates a first access frequency index for each selectable element in the list which corresponds to a number of times the selectable element is selected. Next, the selectable elements are organized on the GUI based upon the first access frequency index generated for each selectable element. In one embodiment, the selectable elements with a higher first access frequency index are placed in first area on the GUI while selectable elements with a lower first access frequency index are placed in a second area on the GUI. As a result, a user can select the selectable elements on a GUI easier when they are organized according to the principles of this invention.

Abstract: A system for distributing clock signals to multiple locations on a chip with minimal skew is disclosed. A series of FIFO control structures, connected in a ring by signal lines of substantially equal length, generates multiple clock signals of equal phase and frequency. The oscillation frequency of the FIFO control ring may be increased to accommodate higher-speed chips, while maintaining synchronization of clock pulses at each stage of the FIFO control ring.