Abstract: The present invention provides a media-independent interface (MII) on a highly integrated network component by implementing the MII interface with a lower pin count, while reducing the timing budget. In another embodiment, the present invention functions to interface MII compatible devices while reducing pin count and the timing budget.

Abstract: A system and method associate each of a plurality of computer applications with a corresponding physical location external to the computer and display a given one of the applications when the user focuses attention on the physical location associated with that application. Preferably the display as a view window in a graphical user interface, and the user has means for moving that window relative to the given application. The computer can be a portable and display device can be head mounted. Preferably an input device enables the user to interact with the given application, and preferably the physical locations bring to mind their associated applications. In some embodiments, an identifier, such as a bar code or a coded transmitter, is placed near each of the physical locations to help detect when the user focuses attention on that particular location. The invention also provides a head mounted unit which projects a visual image to the user wearing it.

Abstract: A network management system is generated by composing a network management model using a bean-based environment and then compiling the model to implement the computer network management system in the bean-based environment. Beans provide a set of properties, a set of methods for performing actions, and support for events and for introspection. The beans are directly able to model the characteristics of components of a system to be modelled. The beans can also be compiled directly to provide the implementation of the model. As a result, the need for a separate environment for modelling a management system from that used to implement that management system can be avoided.

Abstract: An impedance control circuit is provided which controls the output impedance of drivers which are coupled to the impedance control circuit. Accordingly, a desired driver output impedance can advantageously be established and maintained over a wide range of variations in operating conditions and manufacturing processes. Thereby shortening the signal settling time and increasing the attainable signaling frequency.

Abstract: A memory controller provides fast processing of sequential split memory access instructions which include a split write instruction. In a split write instruction, a write address and write request are provided to the memory controller in an initial transaction while write data can be provided to the memory controller in a later transaction. The memory controller includes a sideline buffer, for buffering incomplete write instructions, and memory control logic which ensures proper execution of the sequential memory access instructions. Upon receiving an incomplete write instruction, the memory control logic stores the corresponding write request and write address in the sideline buffer until corresponding write data becomes available. The memory control logic determines if there is overlap between memory space to be occupied by an initial write data block and memory space to be occupied by a subsequent read data block or second write data block, of a read or write instruction respectively.

Abstract: A configuration parameter value access system used in connection with a computer system performs an access operation in connection with a configuration parameter in response to a configuration parameter access request from an applications program. Each configuration parameter access request includes a parameter class identifier, a filename and a parameter identifier. The configuration parameter value access system includes a plurality of configuration file path class lists, each of which has at least one entry, each entry defining a storage subsystem path in the computer system's storage subsystem. A file identifier generator tests successive entries of the configuration file path class list identified by the parameter class identifier to determine whether the storage subsystem contains a file which has the filename provided in the configuration parameter access request along a path defined by an entry.

Abstract: The disclosed system represents an improvement over conventional systems for initializing static arrays by reducing the amount of code executed by the virtual machine to statically initialize an array. To realize this reduction, when consolidating class files, the preloader identifies all <clinit> methods and play executes these methods to determine the static initialization performed by them. The preloader then creates an expression indicating the static initialization performed by the <clinit> method and stores this expression in the .mclass file, replacing the <clinit> method. As such, the code of the <clinit> method, containing many instructions, is replaced by a single expression instructing the virtual machine to perform static initialization, thus saving a significant amount of memory. The virtual machine is modified to recognize this expression and perform the appropriate static initialization of an array.

Abstract: A novel method is taught to quickly and easily produce assember code from a single embedded file which can include high level language code written in any of a number of high level languages interspersed, if desired, among assembler code itself.

Abstract: A system, method, and computer program product for performing an evaluation of a software product wherein a logging module stores in a storage area, such as log file, a description of each loggable test step performed by automated test software. When the automated test is complete or when the software product has filed the automated test, the logging module can write the contents of the log file to a tangible medium so that a user can determine the source of the error or manually reproduce the test steps.

Abstract: A system of executing coded instructions in a dynamically configurable multiprocessor having shared execution resources including steps of placing a first processor in an active state upon booting of the multiprocessor. In response to a processor create command, a second processor is placed in an active state. When either the first or second processor encounter a cache miss that has to be serviced by off-chip cache the processor requiring service is placed in nap state in which instruction fetching for that processor is disabled. When either the first or second processor encounter a cache miss that has to be serviced by main memory, the processor requiring services is placed in a sleep state by flushing all instructions from the processor in the sleep state and disabling instruction fetching for the processor in the sleep state.

Abstract: A distributed filesystem operating on a distributed computing system uses existing local filesystems as building blocks. A cluster filesystem layer is added above the local filesystems to handle functions necessary for a distributed filesystem, such as data coherency. A meta-data stub is developed to flush meta-data from the local filesystem to a storage device. In one embodiment, the meta-data stub is a copy of the flush portion of the meta-data portion of a local filesystem. Additionally, the distributed filesystem supports a plurality of coherency algorithms and variable granularity. A user may select the coherency algorithm that best suits the computer system and granularity that best suits the access patterns of the computer system.

Abstract: A system, apparatus and method for ensuring program correctness in an out-of-order processor spite of younger load instructions being boosted past an older store utilizing a memory disambiguation buffer ("MDB"). The memory disambiguation buffer stores all memory operations that have not yet been retired. Each entry has several fields amongst which are the data and the addresses of the memory operations. An incoming load checks its address against the addresses of all the stores. If there is a match against an older store, then the load must have received old data from the data cache and the load operation is replayed to seek data from the memory disambiguation buffer on the replay. If on the other hand, there were no matches on any older store, the load is assumed to have received the right data from the data cache (assuming a data cache hit). An incoming store checks its address against the addresses of all younger loads.

Abstract: A circuit for controlling a voltage provided to a switching transistor in a voltage conversion buffer which drives a high voltage output with low voltage transistors. The circuit has two elements to it. First, a pull-up circuit pulls the gate of the switching transistor to a high voltage level in response to a first state of a control logic signal. Second, a pull-down circuit pulls the gate of the switching transistor down to an intermediate voltage in response to a second state of the control logic signal. The intermediate voltage is set to be less than the high voltage by no more than approximately the low voltage amount.

Abstract: A method of allocating memory in a multithreaded (parallel) computing environment in which threads running in parallel within a process are associated with one of a number of memory pools of a system memory. The method includes the steps of establishing memory pools in the system memory, mapping each thread to one of the memory pools; and, for each thread, dynamically allocating user memory blocks from the associated memory pool. The method allows any existing memory management malloc package to be converted to a multithreaded version so that multithreaded processes are run with greater efficiency.

Abstract: An apparatus, method and system are disclosed for providing network security for executable code in computer and communications networks, such as providing network security for downloadable and executable Java programming language bytecode. The preferred apparatus embodiment includes a network interface for the reception and transmission of network information, such as an interactive world wide web page; and includes a processor having program instructions to determine whether network information includes a network language keyword, such as a Java applet. When the network information includes such a network language keyword, the processor includes further instructions is further responsive to generate the network language keyword having a distinctive reference to corresponding executable code, such as a distinctive Java class name, and to provide, for transmission by the network interface, the network information in which the network language keyword incorporates the distinctive reference.

Abstract: Disclosed is a printed circuit board that includes selectable structures for attenuating EMI/RFI of replaceable components. In one preferred embodiment, the printed circuit board has a power plane that is subdivided into a plurality of power islands, a ground plane, a plurality of bypass capacitors, and a connector mounted on the printed circuit board for receiving electrical components. Each bypass capacitor is connected between the ground plane and an associated one of the power islands. The connector is connected to at least two selected power island, and the selected power islands are arranged such that when a first electrical component is inserted into the connector, a first one of the selected power islands is automatically connected to a power supply pin of the first electrical component to facilitate attenuation of electromagnetic interference generated by the first electrical component in a first frequency band.

Abstract: The present invention provides methods for storing method frames in a multi-stack memory architecture to provide access to multiple portions of the method frame. In one embodiment, a first frame component of a first method frame is stored in a first stack. A second component of the first method frame is stored in a second stack. A first component of a second method frame is stored in the second stack and a second frame component of the second method frame is stored in the first stack. In some embodiments, the first frame components of the first and second stacks are operand stacks, while the second frame components are arguments and local variable areas.

Abstract: A monitor interface cable for transmitting display data and command data between a computer system and a display monitor preferably including a microcontroller. The monitor interface cable enables both display and command data to be transmitted simultaneously from the computer system to the display monitor. Inside the computer system, data containing the commands written to a particular memory location in a video buffer card is applied to various signal lines located in the monitor interface cable. These signal lines are coupled to the microcontroller located in the display monitor which receives the commands and performs various controlling functions in response. Status information in the form of a command is transmitted back across a second signal line to the computer system where various software programs including drivers receive and process the status information. Display data is simultaneously transmitted over other signal lines also located in the monitor interface cable.

Abstract: An apparatus for cooling an electrical component is disclosed which comprises a sorber containing a sorbent; a condenser in fluid communication with the sorber; an evaporator in fluid communication with both the sorber and the condenser and connected in heat-exchange relation to the electrical component; wherein a sorbate which has been condensed in the condenser is evaporated in the evaporator, thereby absorbing heat from the electrical component, and then adsorbed onto the sorbent; an electromagnetic wave generator; a waveguide coupler for directing the electromagnetic waves to the sorbent; wherein the sorbate is desorbed from the sorbent by the electromagnetic waves and condensed in the condenser; and wherein the desorption of the sorbate from the sorbent is substantially isothermal.

Abstract: A system and method for transferring data over a dedicated memory transfer bus between high and low speed memories of a computer system which share a single real memory address space are disclosed. The dedicated memory transfer bus operates independently from the system bus to avoid any adverse effects on bandwidth and latency of the system bus and to allow virtually any memory hierarchy to be selected. The transfer is controlled by the operating system software upon the execution of instructions issued by the memory management unit. Status information such as "invalid" state is used to direct the transfer.