Abstract: A module consists of a shroud or enclosure attached to a card containing heat-emitting electronic components or to a stack of two or more vertically spaced cards; one or all of which have heat sinks in thermal contact with at least some of the electronic components. The shroud is apertured to control air flow in many directions over the components and heatsinks. A hinge member extends along one edge of the module shaped to be inserted in a slot in a panel to establish a hinge. As the shroud is pivoted about the hinge, horizontal electrical contacts on the panel and at least one card interengage and vertical contacts on one of the cards remote from the hinge simultaneously interengage. The contour of the shroud aids in installing or removing the module.

Abstract: A system for properly delivering an signals in a computer system. A first module is called which waits for a signal to be generated. Upon a signal being generated, the first module is notified of the signal's generation. The first module then directs the signal to a second module, and causes the signal to be delivered to the second module.

Abstract: A bus controller for a computer system. The controller comprises a monitor for monitoring request signals and response signals between a first component and a second component each connected to a bus of the computer system; and a terminator controlled by the monitor to terminate a request from one of the first and second components if a response to the request has not issued within a predetermined period of time.

Abstract: A method, apparatus, and program code visually constructs object-oriented application software to be installed on a distributed object system. The method of the invention includes the following steps. Initially, the method provides a catalog facility which contains components having references to pre-existing objects within a distributed object system. A component is selected from the catalog facility for inclusion in the application software. A part corresponding to the object referenced by the selected component is derived from the selected component. The part is then made available to an application construction environment. In this environment, the part can be linked to at least one other part that also references a pre-existing object in the distributed object system. Graphical facilities are provided within the application construction environment for selecting and defining links among parts.

Abstract: Methods, software, and apparatus for customizing a component for use with an application builder tool are disclosed. A method for customizing a component which has at least one associated property with an associated data type involves obtaining the component, obtaining an editor that is arranged to modify the property, and adding the editor to a customizer that is associated with said component. Then, the property is modified using the editor. In one embodiment, the method further includes configuring the component by implementing the modified property. In another embodiment, the component is an instance of an associated component class, and obtaining the component involves obtaining the component class and creating the instance of the component class. In such an embodiment, each property associated with the component is identified.

Abstract: Methods, systems, and software for efficiently creating virtual file systems including object files which contain data are described. In one aspect of the invention, a method for creating a virtual file system includes retrieving a data file from a file system. A snapshot of the data file is created and converted into an object data file. The converted object data file is linked to at least one other object file. The data file can be concatenated with at least one other data file to create the snapshot. A set of assembly instructions for creating an object file from the snapshot is generated. The assembly instructions include instructions to reserve space within the object file for data contained in the data file. The assembly instructions are converted into an object file and the snapshot of the data file is copied into the reserved space.

Abstract: A method and apparatus for printing a hyperspacial document with multiple pages. Each of the pages is composed in a markup language, and a respective printing element is included in each of the pages. The printing element for a given page is either an indicator of which of the pages is to print after the given page or an indicator that there is no page that prints next. When the header portion of a given page is transferred, it is checked to determine whether it contains a printing element. If the printing element is present, then a command to print the multiple pages is activated. The pages are printed in the order specified by the printing elements.

Abstract: A graphics accelerator using an improved method for evaluating a power function. As part of determining realistic shading for objects in a three-dimensional scene, the Phong technique requires repeated evaluation of the power function D.sup.P, where D is a base value and P is a power value with a fractional component. In one embodiment, a hardware implementation of this function determines the logarithm log.sub.2 (D.sup.P) using a table lookup and a multiplication. An anti-logarithm function is then performed as follows. The logarithm log.sub.2 (D.sup.P) is split into three parts: an integer portion I, a five bit fractional portion F, and a remainder fractional portion R. The desired value D.sup.P is then expressible as 2.sup.I 2.sup.F 2.sup.R. The factor 2.sup.F In2 is found using a 32-entry lookup table. The factor 2.sup.R /In2 is closely approximated by adding 1/In2 to R. Multiplying these two factors and shifting by I bits advantageously produces the desired value D.sup.P.

Abstract: A virtual disk simulator combines memory space from a given process address space in user space to form a virtual disk with contiguous memory space. The virtual disk may be accessed in the same manner as a physical hardware disk. The specific components of the virtual disk simulator are a virtual disk device driver in kernel space and a multi-threaded application running in user space. The virtual disk device driver supports the disk abstraction (e.g. simulation of the virtual disk having what appears to be unlimited disk space) and the multi-threaded application performs actual physical storage management in cooperation with the virtual disk device driver. The virtual disk device driver and the multi-threaded application interact using a special set of communication protocols.

Abstract: An apparatus for mounting an integrated circuit chip to a main printed circuit board is disclosed. The mounting apparatus is particularly suitable for situations in which a cooling device of significant mass is used to cool the integrated circuit chip. In one embodiment, the mounting apparatus mounts the integrated circuit chip onto a daughter or sub-printed circuit (PC) board, attaches the cooling device to the integrated circuit chip, supports the cooling device (as well as the integrated circuit chip and the daughter or sub-PC board) with support members, and uses flexible conductors to electrically connect the daughter or sub-PC board to the main printed circuit board. In another embodiment, the mounting apparatus attaches the cooling device to the integrated circuit chip, supports the cooling device (as well as the integrated circuit chip) with support members, and uses a flexible connection means to electrically connect the integrated circuit chip to the printed circuit board.

Abstract: The invention is a method and apparatus for dynamically loading a gateway server into a client machine if one is needed for the client machine to communicate directly with a program in another domain. In brief summary, when a new machine receives an object reference, this new machine must determine whether it can use the object reference as is for further communications or whether it must try to modify the object reference before using it. The new machine makes this determination by seeing if the front handle of the object reference points to a gateway object that is located on the new machine. If so, then the new machine can use the object reference as is. If the front handle pointer indicates that the designated gateway object is on another machine, then the task is to find or create a new gateway object on the new machine for use in further communications and to modify the object reference accordingly.

Abstract: A high performance microprocessor bus protocol for improving system throughput. The bus protocol enables overlapping read burst and write burst bus transactions to a cache, and interleaved bus transactions during external fetch cycles for missed cache lines. The bus protocol is implemented in a system comprising a CPU, and a secondary cache. The secondary cache comprises an SRAM array cache, and a cache controller. The CPU contains an instruction pipeline and a primary cache system.

Abstract: A processor that executes coded instructions using an instruction scheduling unit receiving the coded instructions and issuing an instruction for execution. A replay signaling device generates a signal indicating when the instruction failed to execute properly within a predetermined time. A replay device within the instruction scheduling unit responsive to the signaling device then reissues the instruction for execution.

Abstract: A low overhead, efficient, and simple protection check circuit is inserted into a data path between a master requester and a target resource such as a memory or input/output device. The master requester initiates a memory request, a pio access request, or a dma transaction directed to the target resource. For example, the master requester may be a processor accessing a memory, a processor performing programmed I/O (pio). Alternatively, the master requester may be a DMA device performing direct memory access of a memory. The protection check circuit is configured at initialization time by an operating system or a privileged software process, then passively monitors all transactions on the data paths, disallowing accesses that fail the protection check operation.

Abstract: Write transactions are conducted by transmitting a first write address from a source device over a first bus on a first clock cycle and transmitting a first data word corresponding to the first write address from the source device over a second bus commencing on a later clock cycle. In order to execute write transactions in this manner, a memory unit is modified to contain a pending write buffer and a memory array. During a write transaction, the address and corresponding data is first stored in the pending write buffer and the data is later transferred into the memory array upon subsequent write transactions. During a read transaction, the read address is compared to the address stored in the pending write buffer. If the read address matches the address stored in the pending write buffer, the corresponding data stored in the pending write buffer is transmitted in response to the read request. If there is no match, corresponding data from the memory array is transmitted.

Abstract: Fees due from transactions in electronic commerce are processed by building a transaction information database with transaction event objects based on events in each transaction. After retrieving fee rules from a fee rule database, a determining step detects if the fee rule applies to information in a transaction event object. Then, if the fee rule applies, a calculating step calculates the fee based on the fee rule and the information in the transaction event object. A fee object for a recipient entity is created based on the fee calculated by said calculating step and is stored in a payment database. An accumulating step sums the payments for a recipient entity from the fee objects in the payment database. The fee rules are general fee rules and specific fee rules. The general fee rules are applied to information in a transaction event object, and a calculating step calculates a general fee based on the general fee rule and the information in the transaction event object.

Abstract: A method and apparatus for allocating registers when compiling code is provided. In response to determining there are insufficient registers associated with a first functional unit of a processor to allocate to a region of code, instructions associated with the region designated for execution on a first functional of processor that may be executed by second functional unit are detected. Those instructions generated for execution on the first functional unit are replaced with the instructions executed on the second functional unit.

Abstract: An apparatus and method for resetting a dynamic logic circuit is disclosed. The apparatus includes an input circuit coupled to a plurality of input nodes wherein the input circuit comprises a plurality of FETs connected between a first voltage node and a dynamic node of a logic circuit. The gate electrode of each input circuit FET is connected to one of the input nodes. Precharged FET is connected between the dynamic node and a second voltage node. The precharge FET is configured to conduct a current for precharging the dynamic node to a predetermined voltage. An inverter is coupled between the dynamic node and an output node. A precharge control circuit is connected in a feedback path between the output node and the precharge FET. The precharge control signal activates the precharge control FET in response to a RESET pulse width and deactivates the precharge FET in response to the voltage on the dynamic node.

Abstract: An apparatus for providing a tactile stimulus to a part of the body of a physical operator when a virtual operator, created by movements of the physical operator, encounters a virtual object defined by a computer. A signalling unit communicates with the computer and emits a signal when the virtual operator encounters a virtual object. A stimulus unit responsive to the signalling unit is disposed in close proximity to a part of the body of the physical operator for providing a tactile stimulus when the virtual operator encounters a virtual object. The stimulus unit may comprise a segment of memory metal which undergoes a martensitic transformation to a different form or a solenoid having a member which moves in response to a signal emitted by the signalling unit. A vibrating member, such as a piezoceramic bender may be used instead of or in addition to the solenoid or memory metal.

Abstract: Low-latency distributed round-robin arbitration is used to grant requests for access to a shared resource such as a computer system bus. A plurality of circuit board cards that each include two devices such as CPUs, I/O units, and ram and an address controller plugs into an Address Bus in the bus system. Each address controller contains logic implementing the arbitration mechanism with a two-level hierarchy: a single top arbitrator and preferably four leaf arbitrators. Each address controller is coupled to two devices and the logical "OR" of their arbitration request is coupled via an Arbitration Bus to other address controllers on other boards. Each leaf arbitrator has four prioritized request in lines, each such line being coupled to a single address controller serviced by that leaf arbitrator. By default, each leaf arbitrator and the top arbitrator implement a prioritized algorithm.