Abstract: A single in-line memory module (SIMM) for memory expansion in a computer system. The SIMM includes a plurality of memory chips surface-mounted on a printed circuit board. The printed circuit board includes a dual read-out connector edge adapted for insertion within a socket of the computer system. One or more driver chips may further be mounted on the printed circuit board and connected to distribute control signals to the memory chips. A full-width data path may further be connected between the dual read-out connector edge and the plurality of memory chips.

Abstract: A method and apparatus for publishing and receiving events to a network. A plurality of "publisher" entities publish information and a plurality of "subscriber" entities request and use the information. Publishers and subscribers are connected to each other through a network. The network is a "store and forward" network whose routing is "content-based." The basic quanta of information is called an "event." Publishers publish events and subscribers subscribe to events that match criteria defined by the subscriber. Publication and subscription are performed asynchronously. Publishers and subscribers do not have direct knowledge of each other. The system receives a published event from a publisher and routes the event to all appropriate subscribers. Each subscriber is guaranteed to receive all events published on the system if, and only if, they match the subscription criteria specified by the subscriber.

Abstract: A dynamic pulse register which uses a standard clock signal and exhibits reduced propagation delay. The dynamic pulse register includes a precharge logic block configured to precharge an evaluate signal and an evaluate complement signal during a precharge phase. During an evaluate phase, a pulldown logic block is configured to discharge either the evaluate or evaluate complement signal in response to a valid data input to the pulse register. A driver logic block is configured to convey a data out signal as the complement of the evaluate complement signal, and a data out complement signal as the complement of the evaluate signal. Either the data out signal or the data out complement signal is thus charged (thereby producing the rising edge of the output pulse) in response to the discharging performed by the pulldown logic block.

Abstract: A host includes a bus cache, a L1 cache and an enhanced snoop logic circuit to increase bandwidth of peripheral bus during a memory access transaction. When a device connected to the peripheral bus starts a memory read transaction, the host converts the virtual address of the memory read transaction to a physical address. The snoop logic circuit checks to see whether the physical address is in the bus cache and, if so, whether the data in the bus cache corresponding to address is valid. If there is a bus cache hit, the corresponding data is accessed from the bus cache and output onto the peripheral bus.

Abstract: A computer system has a program module verifier and at least first and second program modules. Each program module includes a digital signature and an executable procedure. The first program module furthermore includes a procedure call to the second procedure module, a procedure call to the program module verifier that is logically positioned in the first program module so as to be executed prior to execution of the procedure call to the second program module, and instructions preventing execution of the procedure call to the second program module when the procedure call to the program module verifier results in a verification denial being returned by the program module verifier.

Abstract: Methods and apparatus for dynamically compiling byte codes associated with methods during idle periods in the execution of a computer program are disclosed. The described methods are particularly suitable for use in computer systems that are arranged to execute both interpreted and compiled byte codes. In some embodiments, methods to be dynamically compiled are referenced in one or more lists. The lists may be prioritized to facilitate the compilation of the highest priority methods first. In one embodiment, a pair of compilation lists are provided with a first one of the compilation lists being created prior to processing the computer program while the other is created during the processing of the computer program.

Abstract: A slug or plate of copper or some other material having high heat conductivity is attached by an adhesive such as epoxy to a heat-emitting electrical component such as a chip, ASIC, microprocessor, or the like. A heat sink having a base and a plurality of fins upstanding from the base is attached to the slug or plate by screws, nuts or other, preferably detachable, means. The bottom of the base may be formed with a socket to receive the slug. The heat sink may be larger than the slug, thereby improving heat dissipation. When it is necessary to replace the component, the heat sink is detached from the slug and re-used.

Abstract: A computer processor includes a number of register pairs LOCKADDR/LOCKCOUNT. In each pair, the LOCKADDR/LOCKCOUNT register is to hold a value that identifies a lock for a computer resource. When a lock instruction issues, the corresponding LOCKCOUNT register is incremented. When an unlock instruction issues, the corresponding LOCKCOUNT register is decremented. The lock is freed when a count associated with the LOCKCOUNT register is decremented to zero. This scheme provides fast locking and unlocking in many frequently occurring situations. In some embodiments, the LOCKCOUNT registers are omitted, and the lock is freed on any unlock instruction corresponding to the lock. In some embodiments, a computer object includes a header which includes a pointer to a class structure. The class structure is aligned on a 4-byte boundary, and therefore two LSBs of the pointer to the class structure are zero and are not stored in the header.

Abstract: A method and apparatus for accelerating the execution of an object oriented computer program having a plurality of objects. In one embodiment, each of the objects includes an object header and object data which are stored in a memory. Moreover, each of the objects is associated with a corresponding set of methods (or functions). A typical object oriented program only maintains one copy of a method which is accessed by more than one object. However, in the present invention, each method is copied and stored in a memory, such that each object has a dedicated set of methods stored in memory. For example, if a first object and a second object require access to the same method, then a first copy of this method is provided for the first object, and a second copy of this method is provided for the second object. Providing each object with a dedicated set of methods minimizes the levels of indirection required to access the methods, and thereby accelerates the execution of instructions which access the objects.

Abstract: An apparatus and method enables inputs based on a quaternary encoding having high, pulled-up, pulled down and low signal values. The high and low values can be derived from low impedance connections to high and low potential sources, respectively, and the pulled-up and pulled-down signal values can be derived from higher impedance connections to the high and low potential sources, respectively. Discrimination of the first and second levels is performed in two phases. In a first phase a signal level at an input is detected. In a second phase the input is driven towards the inverse of the level detected in the first phase and the level is detected once more. A change in level indicates a high impedance connection to the potential source corresponding to the signal level detected in the first phase. No change indicates a low impedance connection to the potential source corresponding to the signal level detected in the first phase.

Abstract: A heat transmitting slug is attached to a chip or other heat emitting electronic component by an adhesive. A heat sink is mounted on the slug by one or more screws or other fasteners, preferably with thermal grease between the bottom of the heat sink base and the top of the slug. The top of the slug is formed with a longitudinal tongue and the base of the heat sink with a mating groove. Preferably the base of the heat sink is offset upwardly above the groove to resist tendency to fracture under stress.

Abstract: A method for securely accessing a peripheral device at an absolute address is disclosed. A computer program is executed to request from an operating system a memory access object including a procedure executable to address the peripheral device at the absolute address. An operating system procedure is executed to provide the memory access object to the computer program if a value associated with the computer program indicates that the computer program is trusted to perform absolute addressing. If the operating system procedure provides the memory access object to the computer program, the computer program is executed invoke the memory access object procedure to address the peripheral device at the absolute address.

Abstract: A number of methods and apparatus are disclosed for providing a service in a distributed object operating environment. According to some embodiments of the present invention, methods and apparatus for providing a conspiracy among objects in a object operating environment are disclosed. In particular, conspiracies within a distributed object operating environment are contemplated. In general, the present invention teaches mechanisms by which a collection of objects can form a conspiracy wherein objects can both communicate behind the object interfaces and share all resources. In some embodiments, the collection of objects work together to provide a service to clients. According to one embodiment, the objects which are members of the conspiracy may be distributed objects located in separate processes. In some embodiments, objects which are members of the conspiracy are able to perform interactions with one another behind the interface (i.e.

Abstract: A method, in a host adapter circuit configured for coupling a host electronic device with one of a fiber channel loop and a point-to-point communication channel, for receiving data at the host adapter circuit from one of the fiber channel loop and the point-to-point communication channel. The method includes providing a selectable control signal configured for indicating whether the host adapter circuit is coupled to the fiber channel loop or the point-to-point communication channel. The method further includes providing a front-end receive circuit. The front-end receive circuit is configured for coupling with an input data port. The input data port represents one of the fiber channel loop and the point-to-point communication channel. The method also includes coupling the front-end receive circuit with the selectable control signal.

Abstract: A dictionary system has a vendor computer and a plurality of client computers that communicate through the Internet. Each client computer has a word processor program with a spelling checker that utilizes a local main dictionary provided by the vendor and a local customized dictionary containing words added by the user. The vendor computer contains a dictionary of approved words, a database of misspelled words, and a database of requested words. When a user adds a new word to the local customized dictionary, an Internet request is sent to the vendor computer to add the new word to the dictionary of approved words. The user is notified by an Internet message from the vendor computer if the requested word is misspelled. The database of requested words from all users is reviewed periodically and utilized to update the approved dictionary. The updated dictionary is periodically released to the users as an upgrade to the local main dictionary.

Abstract: The present invention provides an interface for a computer system that can drive several different display systems. The interface of the present invention consists of power signals, ground signals, sense signals, programmable signals, and a few miscellaneous signals. The sense signals are driven by each display system that is designed to operate with the interface of the present invention. Each display system drives the sense signals with a code that uniquely identifies the display system. The interface is self-configuring such that the computer system reads the unique code output on the sense signals and correspondingly outputs the proper display information on the programmable signals to drive the display system connected to the interface.

Abstract: A computer bus includes a set of computer bus input nodes to receive a set of computer bus input signals generated by system cards attached to the computer bus. The computer bus input signals are processed by a set of bus bit processors. Each of the bus bit processors includes a digital gate logic circuit to perform a logical OR operation on a subset of the set of computer bus input signals. The subset of computer bus input signals corresponds to the signals carried by a single line of a traditional computer bus. Each bus bit processor generates a bus bit processor output signal. The set of bus bit processors thereby form a set of bus bit processor output signals. The bus bit processor output signals are applied to computer bus output nodes for processing by the system cards in a conventional manner. Thus, the digital gate logic circuits of the bus bit processors execute the function performed by traditional hardwired computer bus structures.

Abstract: A microprocessor is provided with an instruction fetch mechanism that simultaneously predicts multiple control-flow instructions. The instruction fetch unit further is capable of handling multiple types of control-flow instructions. The instruction fetch unit uses predecode data and branch prediction data to select the next instruction fetch bundle address. If a branch misprediction is detected, a corrected branch target address is selected as the next fetch bundle address. If no branch misprediction occurs and the current fetch bundle includes a taken control-flow instruction, then the next fetch bundle address is selected based on the type of control-flow instruction detected. If the first taken control-flow instruction is a return instruction, a return address from the return address stack is selected as the next fetch bundle address.

Abstract: The present invention provides a method and apparatus for using input data to optimize a computer program. Initially, the computer program is divided into one or more logical units of code. Next, a CPU simulator is used to simulate execution of each logical unit using the input data. The output from the simulation is used to generate a first optimization metric value and corresponding state information for each logical unit. In one embodiment, the first optimization metric value and corresponding state information are stored in a first optimization vector. Using well known optimization techniques, the instructions within each logical unit are optimized iteratively until additional optimizations would result in very small incremental performance improvements. A second simulation is performed using the same input data except that this time the optimized logical units are used. This second simulation is used to measure how much the optimizer has improved the code.