Abstract: An environment is emulated in a host environment. Output generated in the emulated environment is displayed in a window of the host environment. The emulated environment's output is in the form of Postscript commands that map to the entire screen. The host environment emulates the Postscript commands an maps the output to a window. Input associated with the window is retrieved by an event driver running in the host environment. Each instance of input is referred to as an event. Each event is translated into an event of the emulated environment by an event driver. A translated event is stored in shared memory for access by a window server. The event driver notifies the window server that one or more events are queued in shared memory. The window server processes the queued events by, for example, transmitting the event to an application running in the emulated environment.

Abstract: A virtual memory lock is placed upon a region of physical memory within a computer system in response to an I/O request through the use of a range lock. Each range lock represents pages of virtual memory that are present and locked in the physical memory. The range locks are cached in memory and used subsequently to process a lock or unlock request, thus avoiding constant locking or unlocking. Regions of memory that are locked, but have no outstanding I/O operations may still have a range lock existing corresponding to that region. If no range lock exists for an I/O request, the virtual memory lock function is called and a range lock is created for that region. If a range lock exists, its usage counter is incremented. Upon notification of the completion of an I/O operation upon a particular region, the usage counter for the range lock corresponding to that region is decremented, and the range lock continues to exist even if there are no outstanding I/O requests for that region.

Abstract: A method for generating non-blocking multiple-phase clocking system for use with domino-type dynamic logic includes receiving a primary clock signal and generating several delayed phases of the received primary clock signal. The number of clock phases equals the number of dynamic logic gates in the circuit. The method provides a first clock phase to the first dynamic logic gate of the circuit, a second clock phase to the second dynamic logic gate and so on. A timing analysis is performed of each logic path in the circuit to determine the arrival time of each critical input signals to each dynamic logic gate. The delay between adjacent clock phase is then predetermined so that each dynamic logic gate enters its evaluation phase before the critical input signal(s) to the particular dynamic logic gate arrives. This adjustment of the clock phases maximizes the logic evaluation speed of the dynamic logic circuit.

Abstract: Snooping is implemented on a split transaction snooping bus for a computer system having one or many such buses. Circuit boards including CPU or other devices and/or distributed memory, data input/output buffers, queues including request tag queues, coherent input queues ("CIQ"), and address controller implementing address bus arbitration plug-into one or more split transaction snooping bus systems. All devices snoop on the address bus to learn whether an identified line is owned or shared, and an appropriate owned/shared signal is issued. Receipt of an ignore signal blocks CIQ loading of a transaction until the transaction is reloaded and ignore is deasserted. Ownership of a requested memory line transfers immediately at time of request. Asserted requests are queued such that state transactions on the address bus occur atomically logically without dependence upon the request. Subsequent requests for the same data are tagged to become the responsibility of the owner-requestor.

Abstract: Arrayed display pixels are coupled such that all row pixels are coupled together by a row conductive element and all column pixels are coupled together by a column conductive element. The row-coupled pixels are driven by first and second row drivers and the column-coupled pixels are driven by first and second column drivers, a total of four drivers in all. The drivers each output time-varying signals of different frequencies. The vertical scan rate is determined by the frequency differential in the signals output by the two row drivers, and the horizontal scan rate frequency is determined by the frequency differential in the signals output by the two column drivers. The absolute frequencies of the four signals are set proportional to the propagation delay of the medium through which the driver signals travel. The invention implements a pixel enabling signal using the beat-frequency difference between two driver source signals that propagate through a pixel string from opposite ends of the string.

Abstract: A remote terminal emulator (RTE) is provided in which substantially all of the time elapsing during an emulated use of a computer system under test is categorized and reported. The time required by the computer system under test to respond to command signals transmitted by the RTE is recorded as a receive time and is measured from completion of the transmission of the command signals to recognition of a pattern specified by the RTE as signifying completion of the response by the computer system under test. As a result, the receive time recorded reflects the time required by the computer system under test to (a) process and carry out the command transmitted by the RTE and (b) transmit response data back to the RTE.

Abstract: A frame buffer system is disclosed that employs non overlapping serial enable signals to access pixel data values from sets of pixel buffers contained in each interleave of a multiple interleave frame buffer according to the attribute data in the frame buffer. The frame buffer system provides circuitry for varying the interleave factor between frame buffer accesses and the generation of corresponding video data. The frame buffer system also provides circuitry for expanding double buffered pixel data values into full addressing for color look-up.

Abstract: An information transfer system includes a transmitter and a receiver for transferring information over a differential communication link. The transmitter circuit includes a plurality of gated driver circuits each associated with one of a plurality separate phases of a clock signal, all of the gated driver circuits having respective outputs connected to a differential driver. Each gated driver circuit receives at a respective input a respective one of a plurality of selected information signals and transmits it over the communication link in response to the associated clock signal phase.

Abstract: A relay mechanism for a network management system permits ready extension and/or modification to an existing system through the use of standard network protocol agents. The relay mechanism uses standard SNMP messaging for both local and remote communication. Only the SNMP relay mechanism is connected to UDP port 161 into listen for management application requests. In operation, the relay examines incoming SNMP requests from a management application and, based on a number of parameters, creates one or more individual smaller SNMP requests which are relayed to the individual agents. When the SNMP relay mechanism receives all the responses to the local SNMP requests, it marshals the information into a single response which is then sent back to the management application.

Abstract: A method and apparatus placing blocks of object code by a compiler. The code placement is done optimally, using a "cut set technique" that uses the "max-flow/min-cut" principle. A preferred embodiment of the present invention divides a source program into blocks and generates a control flow graph (cfg) and a data flow graph (dfg) for the blocks. The compiler then identifies the strongly connected components (sccs) of the dfg and recursively breaks down the cycles in each scc to yield a plurality of directed acyclic graphs (dfg-dag's). The compiler then finds the "minimum cut set" in the cfg corresponding to each dfg-dag and moves the code into blocks in accordance with the minimum cut sets. Lastly, the compiler generates object code for the blocks.

Abstract: A system and method for thermal overload detection and protection for a processor which allows the processor to run at near maximum potential for the vast majority of its execution life. This is effectuated by the provision of circuitry to detect when the processor has exceeded its thermal thresholds and which then causes the processor to automatically reduce the clock rate to a fraction of the nominal clock while execution continues. When the thermal condition has stabilized, the clock may be raised in a stepwise fashion back to the nominal clock rate. Throughout the period of cycling the clock frequency from nominal to minimum and back, the program continues to be executed. Also provided is a queue activity rise time detector and method to control the rate of acceleration of a functional unit from idle to full throttle by a localized stall mechanism at the boundary of each stage in the pipe.

Abstract: A make system includes an overlay make tool for graphical presentation of user-friendly data regarding build operations updating multi-file software architecture. The make system includes a make program building files into executable programs, and a make tool which updates files requiring updating according to an update method relying upon a dependency tree and date stamp information.

Abstract: An efficient method for purging cache memory sub-blocks within a cache memory block is disclosed. The method is particularly applicable to cache memories established on rotating magnetic media, such as a hard disk drive. The method is unique in that it requires absolutely no system overhead when the system is running and the cache is not completely full. When all sub-blocks within the cache memory have been filled, sophisticated, system resource-intensive algorithms are not employed to determine which is the oldest or the least frequently used sub-block of data. Instead, sub-blocks of data are removed in a pseudo-random manner until ample space is available within the cache.

Abstract: An active digital voltage regulator circuit is a two terminal device that is connected in shunt to first and second power supply input lines. The active digital voltage regulator circuit stores energy during times when the local power supply voltage is greater than a predefined voltage, e.g., during times when the parasitic inductances supplement the local power supply voltage. The active digital voltage regulator circuit uses the stored energy to supplement the local power supply voltage during times when the local power supply voltage starts to collapse, e.g., during periods when inductive losses are preventing the power supply from maintaining the local power supply voltage. Consequently, digital active voltage regulator circuit smooths the local power supply voltage by greatly ameliorating the ripple voltages associated with parasitic inductances and resistances. A control circuit within the regulator circuit is a combination of two self-biasing and off-set nulling power supply monitor circuits.

Abstract: A bias circuit that generates a dynamic bias voltage for driving low-voltage transistors in an output buffer that interfaces with high-voltage signals is disclosed. Various circuits have been devised to ensure that no transistor in the bias and the output buffer circuitry undergoes voltages higher than that allowed by the fabrication process, even though the output signal voltage may swing well beyond the tolerable voltage levels. This is accomplished with minimal increase in power consumption and without compromising the speed of operation of the output buffer circuit.

Abstract: A method and apparatus provides data transmission between synchronous systems. One system has a phase locked loop to provide its local clock. The other system has a fixed clock. Fully synchronous bidirectional communication is achieved by adjusting the lengths of the delays between the systems, possibly by adjusting the cable lengths. Deterministic lockstep operation between systems separated by a significant distance is permitted where the communication delays are large compared to a single clock cycle of the systems. Practical tolerances on cable length and signal noise and jitter can be accommodated.

Abstract: On-line memory monitoring system and methods wherein memory subsystem performance is tracked to detect substandard performance and alert a system administrator of the nature of the substandard performance so corrective action can be taken before a system crash and/or automatic reset occurs. A computer system incorporating the invention includes a memory and a processor, wherein the memory storage includes data storage and error correction code storage for each dataword. The system further includes automatic error detection and correction circuitry and software which monitors the occurrence of correction of errors and compares their frequency with the known frequency of soft errors for the memory devices being used to determine whether an alert is to be given and the nature of any such alert.

Abstract: The present invention provides an apparatus and method for repairing or improving the behavior of a tunable circuit of an integrated circuit (IC) when a target parameter exceeds a predetermined range due to a design and/or fabrication problem. The tunable circuit includes one or more tuning controllers for tuning a corresponding number of target circuits. Each tuning controller includes one or more registers and an optional decoder. Each target circuit includes a tunable portion and a functional portion. The functional portion can have one or more of a wide variety of functions including but not limited to logical gates, buffers, signal generators and amplifiers. The selectable parameters of the tunable circuit include timing delays, trip voltages, rise/fall times and/or output impedances. When a circuit designer wishes to tune the target parameter, an appropriate tuning pattern is latched into registers of the tuning controller.

Abstract: An integrated circuit package with heat slug is disclosed. The heat slug is thermally coupled to one or more semiconductor die using a single layer of high conductivity adhesive. The assembly process of this invention includes the steps of initially attaching a temporary heat slug to the back side of a package body, to which one or more semiconductor die are attached. The semiconductor die are then electrically connected to the package body and encapsulated to maintain fixed positions within the package cavity. The temporary heat slug is then moved and a final heat slug is attached to the package body and the back side of the one or more semiconductor dies utilizing a single layer of high conductivity adhesive. The package is compact, has reduced complexity, and is inexpensive to manufacture.

Abstract: A method of encoding and storing locations of bounding boxes of drawing primitives to be rendered on a multi-resolution display that includes a plurality of regions of different resolution, at least one of which is subdivided into a plurality of sub-regions. The method includes steps of dividing the viewable area of the multi-resolution display into four quadrants and encoding only selected attributes of each of the plurality of bounding box locations within only one of the four quadrants of the multi-resolution display. The encoded selected attributes are then stored in a number of locations of a memory.