Abstract: A method for improved speed performance in calculating a checksum by loading groups of data elements into first and second registers. The loaded data elements are then added in parallel, with each data element being added to its corresponding data element in the other register. Thus, multiple additions can be done in parallel, with the result being added to a cumulative result and the process repeated.

Abstract: A computer system and method provide networked computer users with information about which other users are task proximate to the user, thereby facilitating spontaneous communications regarding task-related, or other, issues. The information about other users is displayed in a user interface window on each computer that presents a visual representation of each user who is task proximate to the user operating the computer. Task proximity to other users may change as the user context switches between applications, and the user interface window is updated accordingly. Task proximity is determined individually by different applications. One exemplary system architecture for providing the information includes a person object representing each user, and storing the visual representation of the user. An encounter window on each computer displays the visual representations. A number of encounter-aware applications may execute on each computer.

Abstract: A multiprocessor digital data processing system comprises a plurality of processing cells arranged in a hierarchy of rings. The system selectively allocates storage and moves exclusive data copies from cell to cell in response to access requests generated by the cells. Routing elements are employed to selectively broadcast data access requests, updates and transfers on the rings.

Abstract: The present invention provides a method and system for providing relevance-enhanced image reduction in computer systems. Using such a method and system, information including images can be displayed in a display area that is smaller than the display area for which the information was designed while accurately conveying the overall content of the information. A computer system in which the present invention operates includes a computer connected to a display device and a secondary storage device. A reducer is stored in the secondary storage device for execution by the computer. Additionally, data regarding an image to be displayed on the display device is stored in the secondary storage device. In operation, the computer receives data regarding an image to be displayed from the secondary storage device. The reducer reduces the image by first cropping the image and then scaling the image. Lastly, the computer displays the reduced image on the display device.

Abstract: A compiler is described that generates instructions to execute object-oriented method call invocations in an efficient manner. Specifically, a method dispatch operation distinguishes between those method calls that do not require dynamic invocation from those that do, and optimizes the instructions generated to perform the former. For each object class declaration encountered during compilation, a dispatch array is created. Each dispatch array contains entries for all method calls which can be made to the class, including those implemented in an ancestor class(es), and all protocols adopted by these classes. As each method call is parsed during compilation, if the compiler finds an entry for the calling method in a dispatch table, an instruction to call a non-dynamic method dispatch function is generated. If, on the other hand, no entry for the calling method is found in a dispatch array, the compiler generates a conventional dynamic method dispatch instruction.

Abstract: A method and apparatus for displaying user selectable advertising information or other user selectable informational images on a host computer. In a preferred embodiment, a user accessing the World Wide Web via a browser application is concurrently displayed user selectable advertising information on a predefined portion of the host computer screen. In this embodiment, an advertising application is executed concurrently with the browser application. The advertising application is an object oriented program that includes a data structure for storing methods and data pointers. The methods define the creation of the dedicated portion of the user screen display for displaying the advertising information, methods for selecting the particular information to be displayed, as well as methods for accessing additional information related to the displayed advertisement images.

Abstract: Methods, apparatuses and products are provided for establishing and verifying the authenticity of data within one or more data files. In accordance with one aspect of the present invention, a method for verifying the authenticity of data involves providing at least one data file which includes an identifier and a signature file which includes the identifier for the data file as well as a digital signature. The digital signature is then verified using a computer system, and the identifier in the data file is compared with the identifier in the signature file using the computer system. In one embodiment, the identifier for the data file includes at least one certificate authority, site certificate, software publisher identifier, or a site name, and verifying the authenticity of data involves setting a security level for at least one of the certificate authority, the site certificate, the software publisher identifier, and the site name.

Abstract: A software tool that allows a user to combine a number of smaller documents and then to index the combined documents. A bookfile contains one or more documents, each document containing its own indexing information. The user can drag and drop names of bookfiles into the tool. The invention also compensates for various formats and versions of the documents. A preferred embodiment of the present invention operates on FrameMaker 4.0 documents and can also handle mixed FrameMaker version 3.0 and version 4.0 documents. The software tool combines the documents and generates a master index for all the documents. The software tool also allows the user to specify abbreviations and long titles to use in the index generated for each bookfile.

Abstract: In a networked computer system that includes an omnibus system coupled to a plurality of workstation/computer subsystems, an optimal global reordering of transactions seeking Address Bus access is provided. Access requests are asserted by devices associated with circuit cards, each such card including an address controller, memory, and a coherent input queue. Transactions occurring on the omnibus are loaded into the associated address controller coherent input queue. A global network interface is coupled to the omnibus system and may assert an IGNORE signal, amd includes a table storing all cache lines in the distributed memory system. A transaction seeking to access an address holding invalid data or a remote address is detected by the global network interface, which asserts the IGNORE signal, thus blocking the transaction from loading into the coherent input queue. At a later time when the subject address retains valid data, the interface reissues an identical transaction on the bus.

Abstract: A method and apparatus for quickly copying a first frame region into a second frame region. A video memory array comprising a plurality of video random access memory devices is divided into at least two frame regions. A background image is rendered by a central processing unit into a background frame region within the video memory array. The central processing unit then requests the background image in the background frame region to be copied into a new frame region in the video memory array. A dedicated circuit copies the entire background image in the background frame region into the new frame region. The dedicated circuit operates by using a serial data register within each video random access memory device during the vertical retrace period of a video timing signal. The dedicated circuit performs the background frame copy without requiring any processing resources from the central processing unit.

Abstract: A disk drive device for driving a hybrid optical disk recording medium includes a read head and a read/write head. The read head detects information recorded in a first area of the hybrid optical disk recording medium in accordance with a standard optical format. The read/write head reads or writes information in a second area of the hybrid optical disk. The information recorded in the second area may be written in a different medium, such as a magnetic medium, and/or a different format than the standard optical format. The information recorded in the first area may be set during manufacture of the hybrid disk. On the other hand, information in the second area may be added or changed by the user of the hybrid disk after manufacture.

Abstract: A pipelined instruction dispatch or grouping circuit allows instruction dispatch decisions to be made over multiple processor cycles. In one embodiment, the grouping circuit performs resource allocation and data dependency checks on an instruction group, based on a state vector which includes representation of source and destination registers of instructions within said instruction group and corresponding state vectors for instruction groups of a number of preceding processor cycles.

Abstract: A processor including at least one execution unit generating out-of-order results and out-of-order condition codes. Precise architectural state of the processor is maintained by providing a results buffer having a number of slots and providing a condition code buffer having the same number of slots as the results buffer, each slot in the condition code buffer in one-to-one correspondence with a slot in the results buffer. Each live instruction in the processor is assigned a slot in the results buffer and the condition code buffer. Each speculative result produced by the execution units is stored in the assigned slot in the results buffer. When an instruction is retired, the results for that instruction are transferred to an architectural result register and any condition codes generated by that instruction are transferred to an architectural condition code register.

Abstract: A PCI card is inserted through an I/O opening in a computer panel. On one edge of the card is a cover from one end of which projects a tab. A resilient gasket is attached to the panel to create a flexible EMC seal around the opening. Preferably the gasket is formed of tin-plated beryllium copper. The gasket has alternate staggered spring fingers oriented opposite to the direction of insertion of the PCI card. To retain the gasket the panel is formed with slots at either end and an outward struck projection at the middle. The gasket is formed with a tongue at either end to be inserted in one of the slots and a punched-out opening to receive the projection.

Abstract: The present invention solves the problems associated with the prior art by providing a latency prediction bit (LPB) to indicate the latency with which an instruction should be executed, implicitly indicating whether a data dependency is likely to exist and the likelihood of that dependency causing a hazard. In a processor according to the present invention, an instruction dependent upon a given LDI instruction is issued a given number of machine cycles after that LDI instruction, the number of machine cycles being based on the value of the LPB associated with that LDI instruction. The LPB's value, in turn, depends on whether data will need to be forwarded to the functional unit involved during the execution of LDI instruction. The ability to predict such hazards is important in maintaining a pipeline's throughput and avoiding unnecessary recirculations.

Abstract: A distributed garbage collection system and method is disclosed that is compatible with local ref-count or full garbage collection and that ensures that no local object's storage is deleted by the local garbage collector unless it is certain that there are no actual or potential remote references to that local object. The disclosed system and method are implemented in the context of a transparent distributed object system in which communications between objects in different processes are enabled by dedicated proxy objects that are linked to corresponding remote objects via a pair of transport objects. Additional proxy holder objects and proxy holder proxies ensure that objects for which third-party object references are passed (i.e., where one object in a first process passes a remote object in a second process a reference to a third object in a third process) are not collected until a direct link is established between the remote object in the second process and the third object in the third object space.

Abstract: A network interface card in a networked client computer includes a network interface circuit that decodes and then compares incoming network packet addresses to known address bit patterns, the decoding and comparing circuitry being powered at all times. Receipt and recognition of certain addresses means the client computer must be powered-on, even if manually switched OFF. When such a server-transmitted address is recognized, a power-on signal is issued to a power control unit that causes full operating power to be coupled to the client computer. In this fashion, a server can broadcast power-on signals to a plurality of networked client computers or workstations.

Abstract: A processor is disclosed. The processor includes a processing unit with a plurality of pipelines. Each of the pipelines execute instructions which may define source register values and destination register values from a register file. A plurality of memories is also provided, each associated with one of the plurality of pipelines respectively. A coherency mechanism is provided to maintain coherency among the register values in the plurality of pipelines and their associated memories. In one embodiment, each memory associated with the plurality of pipelines is a register cache. Each register cache stores register values that were just used or will soon be needed by the instructions that have or will be executed on the pipeline associated with the register cache. A variety of coherency mechanisms may be used to transfer register values from register cache to register cache and maintain coherency among the register values in the plurality of register caches.

Abstract: A logic gate includes a plurality of pass gates forming a double rail pass gate XOR or reversing switch providing the same functionality as a conventional XOR gate. Consequently, the pass gate XOR can substitute for XOR gates in circuits such as a selector circuit and decision wait circuit, but with faster responses and fewer transistors than the conventional XOR gate. Each pass gate includes a P-type and an N-type transistor coupled in parallel. A control input and its complement are coupled to the gates of the transistors to selectively pass signals at the input of the pass gate to its output.

Abstract: In the present invention, a method for directing parallel processing computing device to perform the operation of setting a signed value of N bits to an absolute value comprises the steps of: performing an arithmetic shift right of N-1 bit to form a bit mask; performing an exclusive-OR logical operation with the signed value of N bits and the bit mask to form a result; and subtracting the bit mask from the result of the exclusive-OR logical operation to form the absolute value of the signed value of N bits. Further, an apparatus for parallel processing a signed value to form an absolute value comprises: means for performing an arithmetic shift right of N-1 bit to form a bit mask; means for performing an exclusive-OR logical operation with the signed value of N bits and the bit mask to form a result; and means for subtracting the bit mask from the result of the exclusive-OR logical operation to form the absolute value of the signed value of N bits.