Abstract: An improved method and apparatus for distributing transactions among a plurality of groups of processors in a multiprocessor computer system are disclosed. An embodiment of the invention includes the following operations. First, receiving an address request at a first group of processors. The address request is associated with a memory address corresponding to a requested memory page. Next, identifying those of the groups of processors that are interested in the address request and identifying those of the groups of processors that are uninterested in the address request. Thereafter, substantially simultaneously broadcasting the address request to the interested groups of processors and not to the uninterested groups of processors.

Abstract: A cluster implements a virtual disk system that provides each node of the cluster access to each storage device of the cluster. The virtual disk system provides high availability such that a storage device may be accessed and data access requests are reliably completed even in the presence of a failure. To ensure consistent mapping and file permission data among the nodes, data are stored in a highly available cluster database. Because the cluster database provides consistent data to the nodes even in the presence of a failure, each node will have consistent mapping and file permission data. A cluster transport interface is provided that establishes links between the nodes and manages the links. Messages received by the cluster transports interface are conveyed to the destination node via one or more links. The configuration of a cluster may be modified during operation.

Abstract: A CPU (central processing unit) of a computer. The CPU comprises a dispatch controller, a pipeline, a working register file, and an architectural register file. The dispatch controller dispatches instructions for execution and determines whether the dispatched instructions are valid or invalid. The pipeline executes the dispatched instructions using selected operands in the pipeline and generates operands in response. The working register file stores the generated operands before the executed instructions are determined to be valid or invalid by the dispatch controller such that the stored operands may be subsequently selected for use in executing an instruction in the pipeline. The architectural register file stores the generated operands for those of the executed instructions that are determined to be valid by the dispatch controller and transfer operands currently stored therein when one of the executed instructions is determined to be invalid by the dispatch logic.

Abstract: A method and apparatus for pre-processing and packaging class files. Embodiments remove duplicate information elements from a set of class files to reduce the size of individual class files and to prevent redundant resolution of the information elements. Memory allocation requirements are determined in advance for the set of classes as a whole to reduce the complexity of memory allocation when the set of classes are loaded. The class files are stored in a single package for efficient storage, transfer and processing as a unit. In an embodiment, a pre-processor examines each class file in a set of class files to locate duplicate information in the form of redundant constants contained in a constant pool. The duplicate constant is placed in a separate shared table, and all occurrences of the constant are removed from the respective constant pools of the individual class files.

Abstract: A method and apparatus for transforming a source executable code optimized for a source processor into a target executable code optimized for execution on a target processor is provided. Initially, the source executable is converted into a functionally equivalent source executable capable of execution on the target processor. Next, execution performance information for each basic block of code in the functionally equivalent source executable code is collected. Similarly, execution performance information for each basic block of code in an initial target executable code is also collected. As a next step, an optimization metric is generated for each basic block of code within the functionally equivalent source executable code and for each basic block of code within the initial target executable code. These optimization metrics are used to compare basic blocks in the functionally equivalent source executable code with basic block of code within the initial target executable code.

Abstract: A method and system for providing an executable module having an address space for storing program data that is to reside in a read-only storage medium and an address space for storing program data that is to reside in a random access memory is herein described. The executable module represents Java classes that are structured for dynamic class loading. A static class loader is used to modify the class structure to accommodate static loading. The static class loader also identifies methods that contain unresolved symbolic references and data that varies during the execution of the module. These methods and data are identified in order to place them in the address space that resides in the random access memory. The static loader is beneficial in a distributed computing environment having a client computer that has little or no secondary storage thereby requiring applications to run entirely in random access memory.

Abstract: An efficient, cost effective method and apparatus for performing resource allocation of available bit rate (ABR) virtual circuit (VC) in an asynchronous transfer mode (ATM) network includes an explicit rate switch process performed at at least one switch of an ABR VC. The process provides a fast and more accurate computation of the number of active VCs in an ATM network. Furthermore, the fair share allocation is calculated at the switch in a way that is efficient and lends itself easily to implementation in hardware. For example, in one embodiment, the fair share is implemented using a series of counters and registers controlled by a state machine. This simple hardware implementation enables fast convergence to a current final state so that timely accurate resource utilization and allocation to the ABR VCs can be determined.

Abstract: Information is extracted in text form from a graphically oriented application program by commands originating in a test program module. The application module is configured compatibly with the test program module so that it responds with the requested information through the use of a hidden field or window embedded in the application module. The hidden field facilitates communication between the test program and application modules so that the exchanges are transparent to the application user.

Abstract: In a computing system having a plurality of storage devices, notification of an application program of a change of state in a storage device so that corrective action can be taken. A notification module creates and maintains an event queue for storing events corresponding to changes in the state of the storage devices. The notification module indicates to the application programs that events are in the queue. The queue conditions are monitored by the notification for queue maintenance.

Abstract: A computer instruction execution unit includes different execution paths for different categories of instructions. Different execution paths share circuitry. The slower execution paths are pipelined. In some embodiments, all execution paths are pipelined. Fast instructions are executed by a fast execution path. Slower instructions are executed by a slower execution path. Faster instructions immediately following the slower instruction are also executed by the slower execution path not to block the shared circuitry. Consequently, the throughput is increased and the average instruction execution latency is reduced. When a sufficient number of clock cycles accumulate with no instructions started, subsequent fast instructions are executed by the fast execution path. A floating point multiplier is provided in which normalization/denormalization shift amounts are generated in parallel with multiplication of the significands of the operands.

Abstract: A computer housing which includes a chassis that has a first compartment and a second compartment. The first compartment includes a first electronic assembly and a first fan that creates a flow of air through the compartment to create a compartment pressure that is less than an ambient pressure. The second compartment contains a second electronic assembly and a second fan which produces a flow of air that creates pressure within the compartment that is greater than the ambient pressure. The housing also contains an inner wall which separates the first compartment from the second compartment to inhibit air flow between the compartments.

Abstract: In a distributed computer system, a sending node prompts a receiving node to allocate and export to the sending node one or more memory "segments". Each allocated segment is sufficiently large to hold multiple receive buffers whose size fall within a predefined range of receive buffer sizes. Once a segment has been allocated and exported, the sending node allocates receive buffers within the segment, using sequentially contiguous portions for successive receive buffers, without any interaction with the receiving node. Messages are transmitted to the receiving node by remotely writing the data portion of each message to an allocated receive buffer and writing a control message with a pointer to the corresponding receive buffer to a message queue in the receiving node. The receiving node processes messages within the portions of the allocated segments specified by each control message and does not keep track of the used and/or unused portions of each segment.

Abstract: An automated method detects electromigration violations in an integrated circuit design. Starting from the lowest hierarchy of the design so far completed, the parasitic (resistance and capacitance) component values extracted from a layout file are propagated up. Then, at the top-most level, lumping algorithms are employed to calculate the parasitic values for all of the top-most level nets. These values are then passed back down to the lower levels and then at each level, the layout is checked using previously computed parasitic values and EM limits. A peak current, AC-average current and AC-rms current are calculated for every layout, and then compared with the process EM rules for violations, in which the optimum line width and number of vias are specified for each interconnection.

Abstract: An improved memory module for mounting chips. The memory module has a circuit board which is at least partially flexible between a first part and a second part. The first part is mounted horizontally over a second circuit board, such as a mother board. The second part is then bent upward, with the memory chip(s) being mounted on the second part of the circuit board. A heat sink is mounted so that it contacts both the first, horizontal part of the circuit board, and the memory chip(s).

Abstract: A phase error cancellation apparatus captures data bits of a serialized data stream with reduced phase error by aligning a generated clock signal to the data stream. The phase error cancellation apparatus includes a data delay pipe, a clock generator, a clock delay pipe, and a data stream sampling element. The data delay pipe receives the data stream and delays the data bits by a first amount. The clock generator generates a clock signal that the clock delay pipe delays by a second amount. The data stream sampling element receives the delayed data bits and the delayed clock signal, and samples the delayed data bits using the delayed clock signal to recover the data bits from the data stream with reduced phase error.

Abstract: Methods, systems, and computer program products are disclosed for creating, displaying, selecting, updating, and using visual bookmarks. A visual bookmark is a reduced graphical image of a web page that is associated with the URL for that web page. The invention allows the user to view a bookmarked web page by selecting a visual bookmark of the desired page from a plurality of visual bookmarks instead of making a selection from a list of web page titles. One way the visual bookmark is created is when the user decides to add a displayed web page to the user's bookmark list. This causes the displayed image to be captured, reduced, and associated with the web page's URL and title.

Abstract: A method and apparatus for synchronizing the vertical blanking of multiple frame buffers which may exist on the same computer or separate computers for certain applications including stereo display, virtual reality and video recording, which require such synchronization. To obtain the required synchronization one frame buffer is designation as the master. It provides a signal called FIELD that changes state (0 to 1 or 1 to 0) at the start of every vertical sync event on the master frame buffer. All other frame buffers are set to be slaves. Their timing generators sample the master's FIELD signal. When they detect the master's FIELD signal changing state, they set their own internal timing to match to thereby achieve frame synchronization.

Abstract: In one embodiment the present invention provides a method of selecting a selectable element with a character input device from a list of exically unordered selectable elements on a graphical user interface (GUI). Typically, these selectable elements include hypertext links and GUI buttons on the GUI of computer program executing on a computer system. Each selectable element includes a character portion of data which facilitates selecting the selectable element. The method typically begins the selection process when a user enters one or more characters from a character input device. In response to receiving the characters, the present invention inserts each character into a match string. The match string is then compared with the character portion of each selectable element on the GUI. A selectable element is "armed" when the character portion of a selectable element is found which matches the match string.

Abstract: A method for verifying a desired operation of an untrusted memory device is performed under load and includes shadowing read and write operations to the untrusted memory device and to a trusted memory device. The shadowing is performed by concurrently writing data to both the trusted and untrusted memory devices, and concurrently reading data from both the trusted and the untrusted memory devices. All data returned from the trusted and untrusted memory devices in response to the read operations are compared, and if any data compared does not have a same value, a value from the trusted memory device is returned and an error indication is generated.

Abstract: When a processor within a computer system performs a synchronization operation, the system interface within the node delays subsequent transactions from the processor until outstanding coherency activity is completed. Therefore, the computer system may employ asynchronous operations. The synchronization operations may be used when needed to guarantee global completion of one or more prior asynchronous operations. In one embodiment, the synchronization operation is placed into a queue within the system interface. When the synchronization operation reaches the head of the queue, it may be initiated within the system interface. The system interface further includes a request agent comprising multiple control units, each of which may concurrently service coherency activity with respect to a different transaction. Furthermore, the system interface includes a synchronization control vector register which stores a bit for each control unit.