Abstract: Disclosed is a low threshold asymmetric MOS device having a pocket region with a graded concentration profile. The pocket region includes a relatively high dopant atom concentration (of the same conductivity type as the bulk region) abutting either the device's source or its drain along the side of the source or drain that faces the device's channel region. The pocket region's graded concentration profile provides a lower dopant concentration near the substrate surface and an increasing dopant concentration below that surface. This provides a relatively low resistance conduction path through the pocket region, while allowing the device's threshold voltage to be somewhat higher at the pocket region. The asymmetric device can also include a counter dopant region located beneath its substrate surface. This forces current to flow in the substrate but just above the region of high counter dopant concentration, where the resistance is relatively low.

Abstract: An interprise computing manager in which an application is composed of a client (front end) program which communicates utilizing a network with a server (back end) program. The client and server programs are loosely coupled and exchange information using the network. The client program is composed of a User Interface (UI) and an object-oriented framework (Presentation Engine (PE) framework). The UI exchanges data messages with the framework. The framework is designed to handle two types of messages: (1) from the UI, and (2) from the server (back end) program via the network. The framework includes a component, the mediator which manages messages coming into and going out of the framework.

Abstract: In a computer system including a packet-switched bus, a method for requesting transactions such that memory accesses are initiated quickly. A master transmits a first portion of a transaction request packet having multiple portion. A memory controller receives the first portion of the transaction request, which includes a row address portion of a memory address. The memory controller initiates a memory access by applying a row address strobe signal to the row of the memory location in response to receiving the first portion of the request packet, and the master transmits any remaining portion of the transaction request. After the full memory address has been received, it is determined whether data stored at the memory location is to be read from a source other than the memory location. The memory controller aborts the memory access by inhibiting assertion of a column access strobe signal to the memory location if the data is to be read from a source other than the memory location.

Abstract: A network manager automatically sends certain requests in response to selected events generated by network devices. When a device generates an event, the network manager can send stop requests to the device; send different event requests to the device; or send the same event request to the device, but over a different path. The stop request is sent to cut down on network management traffic. The different event requests can be sent to determine why the event was generated by the device in the first place. The same event request can be sent over a different path to determine whether a problem exists with the device itself or with the path to the device.

Abstract: A method and apparatus that allows a computer system to trust both program and data files without the intervention of the user and without the possibility of circumventing the model of trust. A file system incorporates two levels of validation for programs and data. A first level of validation specifies sources that the user has decided are trustworthy or untrustworthy. A second level of validation specifies sources that the system itself considers trustworthy or untrustworthy. For data to be acceptable, it must be acceptable to both levels of checking. In addition, both the user and the system can specify multiple acceptable signatures and further allows various ones of the multiple signatures to have different levels of access to the system.

Abstract: A method and apparatus for implementing proportional sharing in a single processor system and/or in a multi-processor system. The invention can also implement proportional sharing in a system that executes multi-threaded computer programs. The invention uses the metaphor of "tickets." Each process in the system has a number of tickets and each ticket entitles the process to use a processor for a period of a time quantum. The operating system allocates the processor(s) first to the process with the highest number of tickets. As each process (or thread) finishes being executed for a predetermined amount of time, the tickets of that process/thread are adjusted accordingly and a new process (or thread) is chosen for execution. Tickets can be allocated to each process in the system. Alternatively, tickets can be allocated to each process and shared by all threads of the process. Alternatively, tickets can be allocated to a group of processes and shared by all processes within the group.

Abstract: A synchronizer comprised in part of a series of flip-flops is used to deterministically transfer data between clock domains during system test. Flip-flops in the clock domain operating at a higher clock frequency have a clock enable signal. The clock enable signal is defined so as to approximately align the enabled rising clock edges of the faster clock signal with the falling edges of the slower clock signal. This approximate alignment provides a timing window of one half period of the slower clock for the data to stabilize at the input of a flip-flop in the faster clock domain before it is sampled. This ensures deterministic transfer of data. Data flow control circuitry can be used to provide a ready signal to the faster clock domain to indicate that the synchronizer is available to transfer a synchronization signal. After testing is complete, the synchronizer can operate in an application mode wherein one or more of the clock enable signals is set to a continuous high level to minimize latency.

Abstract: The present invention provides a method and system for creating a test script. The invention begins processing when a user requests the automatic creation of a test script. When the user next enters data on a graphical user interface, the data is sent to a display server which manages the input and output on the graphical user interface. The display server creates an event corresponding to the type of input entered on the graphical user interface.In order to examine the context within which the event occurred, the present invention interposes a new version of a routine into the system so that the new routine is called when the GUI program attempts to retrieve the event from the display server buffer. Interposing ensures that the new version of the routine will be invoked before the original version of the routine.

Abstract: An apparatus and method for translating a virtual address to a physical address utilizing an address translation unit implemented within a network interface card is described. The address translation unit of the present invention is utilized in a computer system. The computer system comprises a first bus; processors with embedded caches and memory coupled to the first bus; a second bus; a network logic coupled to the second bus, wherein the network logic includes an address translation unit; and a bus bridge coupled to the first bus and to the second bus.

Abstract: A method and apparatus for interfacing between a Segmentation and Reassembly (SAR) circuit and an ATM Cell Interface is disclosed. The interface circuit comprises a transmit FIFO and a receive FIFO. The transmit FIFO transfers data from the System and ATM Layer Core in the SAR circuit to a Cell Interface block, which in turn dispatches the data to the ATM Cell Interface. The receive FIFO transfers data received from the ATM Cell Interface via the Cell Interface block, to the Core. Various interface signals provided between the Core and the transmit FIFO, the transmit FIFO and the Cell Interface block, the Core and the receive FIFO, and the receive FIFO and the Cell Interface block, are used to coordinate data transfer. The interface circuit insulates the Core from the ATM Cell Interface, allowing the Core to operate independently from ATM Cell Interface specifics.

Abstract: A system, method and computer program product comprising a storage manager independent configuration interface translator which requests an opaque listing of the available storage devices from an associated metadisk driver and determines a subset of the listing meeting a preselected search criteria. The resultant opaque listing is then converted to a non-opaque format listing for presentation to a user of the computer system in a desired format such as through a command line or graphical user interface. A notification mechanism is also provided that presents information about storage devices which have in some way changed while in use.

Abstract: A multiprocessing system having a plurality of processing nodes interconnected by an interconnect network. A home agent is configured to service multiple requests simultaneously. A transaction blocking unit is coupled to a home agent control unit for preventing the servicing of a pending coherent transaction request if another transaction request corresponding to the same coherency unit is already being serviced by the home agent control unit. The transaction blocking unit is further configured such that read-to-share transaction requests in a NUMA mode do not block other read-to-share transaction requests in the NUMA mode.

Abstract: A method and apparatus for performing reliable data transfer operations over a global computer network are provided. This is accomplished by transmitting data stored on a first computer system connected to the global computer network to a second computer system connected to the global computer network, sending a receipt acknowledgment signal to the first computer system when the data is received on the second computer system, monitoring acknowledgment signals received by the first computer system, and automatically transmitting the data via facsimile if the receipt of the data is not acknowledged within a predetermined time period. In addition, a paging signal is automatically transmitted to a the business partner to indicate that the data has been transferred by facsimile. Unlike prior art techniques, in which data transfers are performed in batch off-line, embodiments of the invention allow for secure data transfer operations to be performed on-line in real-time.

Abstract: In a control block design methodology, control block design proceeds without the inclusion of scan functionality until the functional design specifications are met. After meeting the functional design specifications, a scan insertion tool is executed to automatically insert scan functionality. The insertion is performed in such a manner that the functional cells within the control block are not perturbed. Therefore, functional timing may be minimally affected, if at all. In one embodiment, a scan enable buffer is inserted at the end of each row in the control block. Flops (or other scannable storage devices) within the row are connected to the scan enable line provided by the scan enable buffer within the row. Additionally, flops are connected into a scan chain on a row-by-row basis, minimizing the length of the wires connecting the scan chain. If a particular scan chain wire exceeds a length which will meet scan timing requirements, a scan chain buffer can be inserted as well (e.g. at the end of the row).

Abstract: A clock recovery system that allows recovery of a clock signal from a high speed, potentially small amplitude data stream. The invention uses a normally avoided property of a non-linear oscillator in the clock recovery system in order to lock the oscillator in phase to an incoming signal. This property relates a characteristic of an oscillator that an oscillator amplifies noise near its inherent frequency; and if the noise is large enough, the oscillator squelches the inherent oscillator frequency signal and outputs a signal locked in frequency and phase to the noise. The clock recovery system comprises a processing circuit, an oscillator, and a control circuit. The processing circuit processes an input data stream to generate a current signal as a first control signal based on data transitions in the input data stream. The first control signal is a "noise signal" to the oscillator.

Abstract: An extraction tool for extracting a module that is detachably connected to a mounting substrate includes a fixed plate that is vertically supported over the module to be extracted. A movable plate is arranged below the fixed plate and a screw is inserted in central openings in each of the fixed and movable plates. A pair of vertically extending side panels are connected at one edge by a hinge to opposite sides of the movable plate. The opposite edge of the respective side panels are used to grip the module to be extracted. A spring biases the side panels inwardly. A rotatable handle is arranged above the fixed plate and is connected to the screw. Lateral rotation of the handle causes a corresponding axial rotation of the screw for moving the movable plate in a vertical direction.

Abstract: An improved hybrid dynamic-binding system for switching between static binding and dynamic binding of function calls provides static binding for function calls when the function is unambiguous, and when the function becomes ambiguous at runtime, this system switches to dynamic binding, without recompiling the code of the function call, thus improving performance over conventional systems. The system performs this functionality by inserting a placeholder into a statically bound function call so that when the statically bound function call needs to be converted to a dynamically bound function call, the placeholder can be overwritten to perform the conversion without having to recompile the code.

Abstract: A bus line is provided with broadly distributed signal termination by using switched termination logic where the pull up resistance of a driver corresponds to the characteristic impedance of the line and the pull down resistance of the driver corresponds to the number of drivers coupled to the line. Accordingly, signals being transmitted over the bus suffer relatively few reflections thus advantageously producing a shortened signal settling time, thereby increasing the attainable signaling frequency.

Abstract: A computer system which exhibits increased performance for stereo viewing. The computer system includes a display screen, a bus for transferring data, a memory coupled to the bus for storing geometric primitives and left and right view transformation matrices. Furthermore, the computer system includes a processor coupled to the bus, wherein the processor is configured to enable stereo mode and to execute an application for rendering objects on the display screen in the stereo mode. The computer system also includes a graphics accelerator coupled to the bus. The graphics accelerator includes a buffer for storing a received geometric primitive to be rendered in stereo mode, as well as memory for storing the left and right view transformation matrices. The graphics accelerator also includes a transformation unit which is configured to generate a first transformed geometric primitive in response to the received geometric primitive and the left view transformation matrices.

Abstract: The present invention provides a phase locked loop (PLL) clock generator for a digital system. The PLL clock generator is capable of an instantaneous transition between a high frequency and a low frequency, corresponding to an active mode and a slow mode, and vice versa The PLL clock generator includes a phase locking circuit, a frequency changer coupled to the output of the phase locking circuit, and a frequency controller coupled to the frequency changer. The frequency changer is capable of instantaneously changing the frequency of a first clock signal received from the phase locking circuit. The frequency controller is responsible for controlling the frequency at the output of the frequency changer. The frequency controller is responsive to a control signal which is used to transition the PLL clock generator from an active mode to a slow mode and vice versa In one embodiment, the phase locking circuit generates the first clock signal in response to a reference clock signal and a feedback clock signal.