Abstract: A circuit for generating the sticky-bit includes a first encoder, a second encoder and an adder circuit. The first and second encoders respectively provide encoded values representing the number of trailing zeros in the first and second operands of the multiplication operation. The adder receives the encoded values from the encoders and a constant. The constant represents the number of bits used in determining the sticky-bit. The adder circuit then adds the encoded values together to generate a sum representing the number of trailing zeros in the resultant. The adder circuit then compares the sum to the constant. If the sum is larger than the constant, then the sticky-bit is given a value of zero and, conversely, if the sum is smaller than the constant, the sticky-bit is given a value of one.

Abstract: A fully depleted SOI device includes a semiconductor substrate and a conductive well of a first conductivity type formed in a principal surface of the semiconductor substrate. An insulating layer is formed along the principal surface of the semiconductor substrate and extends across the conductive well. A transistor is formed on the insulating layer such that the insulating layer is interposed between the transistor and the semiconductor substrate, with the transistor including source and drain regions of the first conductivity type formed on the insulating layer, a channel region of a second conductivity type formed on the insulating layer and aligned over the conductive well, and a gate electrode aligned over the channel region. A metal contact is connected to the conductive well for applying a reverse bias potential to the transistor.

Abstract: A method for redirecting communication on a network between a client and a network resource includes executing a software program, the software program configured to listen to at least one communications port of the client during the communication session, the software program redirecting a message received on the communications port to the network resource.

Abstract: A method for expanding and contracting a window panel to uncover the panel's content to the user without resize other panels and without reformatting their content, is described. A user chooses a window panel by moving a pointer to that panel. If there is content in that panel not shown to the user, the panel expands to show the entire content. If expansion is not necessary initially, the system waits to see if any actions by the user require expansion. Upon expansion at any stage, portions of neighboring window panels are covered instead of the neighboring panels contracting and reformatting their content. Once the pointer is moved out of a window panel, the panel contracts to its default or original size and the expansion process occurs for a newly entered panel. Also described is the process of determining the maximum expansion size of a window panel and the "rolling out" and "rolling in" characteristic of the expansion and contraction process.

Abstract: The present invention provides a method and system for achieving high availability in networked computer systems. The computer system includes a client node, two server nodes, and a secondary storage device. One server node includes a primary replica, and the other server node includes a secondary replica. In order for the client node to request a service that involves the secondary storage device, the client node sends a request for the service to the primary replica. The primary replica performs an intention phase of the service and sends a checkpoint message to the secondary replica. The secondary replica updates the state of the secondary replica and sends an acknowledgement message to the primary replica. The primary replica performs the service, sends a reply message to the client node, and forgets about the request. The client node resumes execution and asynchronously sends a forget message to the secondary replica. Upon receiving the forget message, the secondary replica forgets about the request.

Abstract: A memory device is presented including a memory array having both trench capacitor and stacked capacitor DRAM cells. The trench and stacked capacitor DRAM cells are arranged in a configuration which achieves increased cell density while providing adequate electrical isolation between cells. The increased density of the memory array results in an increase in operational performance and a decrease in cost on a per storage bit basis. The memory array includes electrically conductive bit and word lines. The bit lines are arranged in vertical columns. The trench capacitor DRAM cells are arranged in pairs and aligned along the bit lines. Each pair of trench capacitor DRAM cells shares a common electrical contact to the bit line to which the pair is aligned. Capacitors of the stacked capacitor DRAM cells may be formed above the bit lines.

Abstract: A receiver is provided which quickly and efficiently recognizes signals by including with the receiver a resolving circuit which is coupled to a node control circuit which determines the signals to be recognized. The resolving circuit can operate with supply voltage levels as low as one threshold voltage. Also, the signal hold time can be made very small depending on the sizing of certain transistors. Other advantages include reduced power consumption, high speed operation, good rejection of input noise and power supply noise, ability to resolve small (e.g., 1.0 mVolt) voltage differences, and the ability to function with a variety of types of drivers, including HSTL, DTL and PECL.

Abstract: In certain systems where a series of stages are employed, it is desirable to control the action of a stage without possibility of interference form adjacent stages. A circuit of linked mutual exclusion elements is described which renders inactive the stages adjacent to an active stage, or inhibits action in a stage if any of its neighbors is active. This ensures that the stages adjacent to an active stage remain inactive, thereby avoiding problems associated with input events changing while an adjacent stage is active.

Abstract: The outcome of a given branch instruction is predicted using early and late branch history addressing modes. In an early addressing process, a first subset of bits from a branch history register is used to first address a branch history table to obtain a plurality of candidate predictions. In a late addressing process, a second subset of bits from the branch history register is used to again address the branch history table to select one of the plurality of candidate predictions, the second subset of bits including additional branch history information loaded into the branch history register subsequent to the early addressing mode. In this way, more recent branch history information is used to predict the outcome of the given branch instruction.

Abstract: A method for resolving differential signals is provided which quickly and efficiently recognizes signals by resolving differences between the signals using a resolving circuit which is powered by a clock signal. The resolving circuit operates with supply voltage levels as low as one threshold voltage. Also, the signal hold time can be made very small depending on the sizing of certain transistors. Other advantages include reduced power consumption, high speed operation, good rejection of input noise and power supply noise, ability to resolve small (e.g., 1.0 mVolt) voltage differences, and the ability to function with a variety of types of drivers, including HSTL, DTL and PECL.

Abstract: A voltage controlled current source provides controlled current to a current controlled oscillator in a high frequency phase-locked loop clock generator. The voltage controlled current source receives a first control signal and a set of second control signals indicative of a phase difference between the output signal of the clock signal generator and a reference frequency. It uses those control signals to adjust the current-controlled oscillator. A level shifter coupled to the current-controlled oscillator amplifies the oscillator signals to full rail and adjusts the duty cycle at its output to 50% to produce the clock signal generator output signal.

Abstract: In a processor speculatively executing instructions which specify logical addresses, a method and apparatus for speculatively converting logical addresses to physical addresses. The processor has a register window movable within a register file, a window pointer register maintaining a value corresponding to the location of the window in the register file, a speculative window pointer register maintaining a speculative value of the window pointer register. A controller identifies an instruction expected to modify the value in the window pointer register, and in response to identifying the instruction the controller modifies the speculative value. A mapper, coupled to the speculative window pointer register, converts the instruction specified logical addresses to physical addresses based on the speculative value contained in the speculative window pointer register.

Abstract: A number of multiple-band pixels are stored in a number of data words and the multiple-band pixels are merged and sorted such that all components of each band of the pixels are stored contiguously and in the order in which the multiple-band pixels are originally stored in the data words. As a result, the pixels are converted from an interleaved format to a planar format. The data words are essentially divided in half and the halves are merged such that the pixel components are interleaved in a number of intermediate data words. By repeatedly dividing the intermediate data words in half and merging the respective halves, the components of all the pixels corresponding to each band are stored contiguously in a number of data words. The contiguous components of each band are sorted such that the components of each band are stored in the order in which the multiple-band pixels are originally stored in the data words.

Abstract: PCI cards are plugged into vertical risers, the lower edges of which have been plugged into a motherboard. This involves a considerable force being applied to the riser card, both during insertion and removal, and may damage the card or the underlying motherboard. A support for the top edge of the riser card clips onto the upper end thereof. Rearward extensions of the support are gripped by tabs struck out of a wall of the enclosure.

Abstract: A method and apparatus is provided for determining and resolving cache conflicts among data arrays that are stored in the main memory of a computer system in which the main memory is coupled with a memory cache that is coupled in turn with a microprocessor. According to the method of the invention, a cache shape vector that characterizes the size and dimension of the cache is determined under computer control. A determination of at least one cache conflict among the arrays stored in the main memory is then determined, in addition to the conflict region in the cache for the conflicting arrays. A padding value is then determined for the arrays stored in the main memory, and the memory locations of the arrays are adjusted in accordance with the padding value to prevent cache conflicts when the data from the conflicting arrays is transferred from the main memory into the cache.

Abstract: A method for creating a virtual device driver that runs under both Windows 3.x and Windows 95 operating systems is disclosed. There are two basic obstacles to be overcome in creating a virtual device driver VxD that will operate under both Windows 95 and Windows 3.x. The first obstacle, that of identificational incompatibility, is cured by disguising a Windows 95 compatible driver as a Windows 3.x compatible driver. This is done by renaming the Windows 95 driver with a file name having the three-character extension "386". The version number within a Device Descriptor Block must also be changed in order to effect a total disguise. Once the identificational incompatibility has been cured through the aforementioned steps, Windows 3.x will load the Windows 95 driver. The second obstacle, that of partial functional incompatibility, is cured by appending additional logic and supplementary Windows 3.x emulation routines to the Windows 95 driver. The logic works in the following manner: Whenever a Windows 3.

Abstract: A system and method for many-to-many failover and load balancing establishes a plurality of service groups for providing desired computing services. Each service group comprises a plurality of hosts, and each host within the service group is available to perform the computing services for which that group as a whole is responsible. Each host may belong to a plurality of service groups. Each operational host within a service group transmits periodic messages to each other host within the service group advising of the status of the transmitting host. A leader host evaluates the periodic messages and, where appropriate, dynamicall reassigns responsibility for particular computing services to a host within the group. The reassignment can be due either to failover or load balancing.

Abstract: An apparatus and method for facilitating the sharing of memory blocks between a computer node and an external device irrespective whether the external device and the common bus both employ a common protocol and irrespective whether the external device and the common bus both operate at the same speed. Each of the memory blocks has a local physical address at a memory module of the computer node and an associated memory tag (Mtag) for tracking a state associated with that memory block, including a state for indicating whether that memory block is exclusive to the computer node, a state for indicating whether that memory block is shared by the computer node with the external device, and a state for indicating whether that memory block is invalid in the computer node. The apparatus includes receiver logic configured to receive, when coupled to the common bus of the computers node, memory access requests specific to the apparatus on the common bus.

Abstract: The integer execution unit (IEU) of a central processing unit (CPU) is provided with a graphics status register (GSR) for storing a graphics data scaling factor and a graphics data alignment address offset. Additionally, the CPU is provided with a graphics execution unit (GRU) for executing a number of graphics operations in accordance to the graphics data scaling factor and alignment address offset, the graphics data having a number of graphics data formats. In one embodiment, the GRU is also used to execute a number of graphics data addition, subtraction, rounding, expansion, merge, alignment, multiplication, logical, compare, and pixel distance operations. The graphics data operations are categorized into a first and a second category, and the GRU concurrently executes one graphics operations from each category.

Abstract: Methods and apparatuses for altering the appearance of an icon box when an event effecting the icon box occurs are disclosed. In one embodiment, a pointer entering an icon box or exiting an icon box is detected and an icon property is set accordingly. Also detected is an icon being set to activate its underlying function and the actual activation of an icon's underlying function. Another icon property is set based on whether an icon is set to be activated or has been activated. A repaint procedure is used to retrieve a new icon image and replace the image in the icon before the event occurred. The repaint procedure uses an icon label and the icon property states to determine which image to retrieve and place in the icon box. The repaint method retrieves an image from a plurality of images reflecting different states of the icon. The icon is also capable of communicating any events effecting it to its parent object, such as a toolbar, thereby allowing the parent object to behave in an appropriate manner.