Abstract: A system, method and computer program product which determines the relative performance of a local cache and renders the resultant performance increase (or in certain circumstances, the decrease) in cache performance of a stand-alone computer or networked "client" perceptible to the user in an especially intuitive manner. By accurately tracking and factoring in the times and amounts of data read from one or more source locations and the cache, the amount of time required to execute "read" operations without the cache can be determined. By dividing this time period by the actual time to execute the "read", the true relative performance of the cache may be determined.

Abstract: Several designs of a stage for use in a FIFO pipeline are disclosed. Each stage includes a latch that is capable of latching a data element and capable of transitioning between a transparent state and an opaque state. The stages also include a control circuit capable of announcing the availability of the data element to the next stage as soon as the data element has propagated through the latch and without any latching or unlatching action of the latch prior to the announcement of the availability of the data element. In other words, if the latch of a stage is transparent and receives a signal Ri from the previous stage, the control circuit of the stage generates signal Ro after receiving signal Ri, thus enabling the next stage to latch the data element before the current stage has itself latched that data element.

Abstract: A multi-layer switch search engine architecture is provided. According to one aspect of the present invention, a switch fabric includes a search engine, and a packet header processing unit. The search engine may be coupled to a forwarding database memory and one or more input ports. The search engine is configured to schedule and perform accesses to the forwarding database memory and to transfer forwarding decisions to the one or more input ports. The header processing unit is coupled to the search engine and includes an arbitrated interface for coupling to the one or more input ports. The header processing unit is configured to receive a packet header from one or more of the input ports and is further configured to construct a search key for accessing the forwarding database memory based upon a predetermined portion of the packet header. The predetermined portion of the packet header is selected based upon a packet class with which the packet header is associated.

Abstract: A variety of methods and apparatus for managing a database in a object oriented environment are disclosed. According to the present invention, a database is provided which includes a database cache and a persistent database portion. Clients of the database are able to write quickly and asynchronously to the database cache, which may be located in transient memory such as random access memory. In order to maintain consistency between the state of the client and the state in the database, the data in the database cache must be written to the persistent database portion. In preferred embodiments a time commit thread executing in a computer process will, in single operations performed at predetermined intervals and when predetermined conditions are met, commit the data in the database cache into the persistent database portion. Thus through the strategies of the present invention, a single client database can have multiple clients.

Abstract: An integrated circuit assembly includes an integrated circuit die having a first face, a second face and a perimeter. The second face bears a plurality of electrical contacts. A substrate is coupled to the die and has a first surface and a second surface facing in a different direction from the first surface. The substrate has a plurality of layers between the first and the second surfaces, at least some of the layers having one or more electrical traces. A compartment extends from the second surface through a plurality of the layers and has surfaces defining an inner chamber including a device interface surface. A plurality of electrically conductive vias extend through a plurality of the layers and at least two non-intersecting vias extend from the first surface and are coupled to electrical contacts of the substrate and to the device interface surface.

Abstract: Transmission rates of 1 Gb/sec. at up to at least 200 m diameter distances are achieved in an Ethernet environment by functionally decoupling frame size to network roundtrip time. This decoupling is achieved by extending the duration of the minimum size event to exceed the network roundtrip time. This extension of the carrier event is made without extending the data field and without altering the frame check sequence. Code implementing the media access control layer and reconciliation layer at the transmitting and receiving end of the network is modified such that at 1 Gb/sec. half-duplex, non-data symbols are appended to the end of short packet frames. The collision window is extended to include these symbols, which extension symbols are also included in fragment discard calculations. The extension is removed, however, before checking the frame check sequence, and before passing the frame to logical link and control.

Abstract: One embodiment of the present invention provides a method and an apparatus for predicting the target of a branch instruction. This method and apparatus operate by using a translation lookaside buffer (TLB) to store page numbers for predicted branch target addresses. In this embodiment, a branch target address table stores a small index to a location in the translation lookaside buffer, and this index is used retrieve a page number from the location in the translation lookaside buffer. This page number is used as the page number portion of a predicted branch target address. Thus, a small index into a translation lookaside buffer can be stored in a predicted branch target address table instead of a larger page number for the predicted branch target address. This technique effectively reduces the size of a predicted branch target table by eliminating much of the space that is presently wasted storing redundant page numbers.

Abstract: In a multiprocessing computer system, a schedulable process entity (such as a UNIX process, a Solaris lightweight process, or a Windows NT thread) sets a memory flag (sc.sub.-- nopreempt) before acquiring a shared resource. This flag tells the operating system that the process entity should not be preempted. When it is time for the process entity to be preempted, but sc.sub.-- nopreempt is set, the operating system sets a flag (sc.sub.-- yield) to tell the process entity that the entity should surrender the CPU when the entity releases the shared resource. However, the entity is not preempted but continues to run. When the entity releases the shared resource, the entity checks the sc.sub.-- yield flag. If the flag is set, the entity makes an OS call to surrender the CPU.

Abstract: A single-ended match sense amplifier is provided for use in a translation lookaside buffer. The translation lookaside buffer includes a CAM array for storing x bit virtual addresses. The CAM array has n rows and x columns of CAM cells, each CAM cell having input node for receiving a virtual address bit signal, and a CAM miss/match node. N rows and minor sense amplifier circuits are coupled to n major sense amplifier circuits via n major sense lines. Each minor sense amplifier circuit has a minor sense input node, and a minor sense miss/match node. Each minor sense line is also coupled to at least two CAM cell miss/match nodes. A minor sense precharging device is coupled to each minor sense line. The minor sense precharging device selectively conducts current to precharge the minor sense lines to a first predetermined voltage. Each of the major sense amplifiers has a major sense input node, and a major sense miss/match node.

Abstract: A microprocessor is provided with an instruction fetch mechanism that simultaneously predicts multiple control-flow instructions. The instruction fetch unit farther is capable of handling multiple types of control-flow instructions. The instruction fetch unit uses predecode data and branch prediction data to select the next instruction fetch bundle address. If a branch misprediction is detected, a corrected branch target address is selected as the next fetch bundle address. If no branch misprediction occurs and the current fetch bundle includes a taken control-flow instruction, then the next fetch bundle address is selected based on the type of control-flow instruction detected. If the first taken control-flow instruction is a return instruction, a return address from the return address stack is selected as the next fetch bundle address.

Abstract: A method and apparatus that allows a Web page designer to specify tooltips for his Web page. Tooltips are text areas that display automatically when the user places the cursor over predetermined text on a display device. The invention also enables Web browser software to display the tooltips specified by the designer. The HTML format extension allows a Web page designer to specify the text over which the user must place the cursor to activate tooltips. The HTML extension also allows the designer to specify the tooltip text that will be displayed when the cursor reaches the specified text. Using the present invention, the designer only needs to specify tooltips for any given information once per page, even though the displayed information may appear multiple times on the Web page.

Abstract: Translation between a character encoding scheme used by an application and a font encoding scheme used by a character drawing routine may be controlled dynamically so as to accommodate multiple possible font encoding schemes. Accordingly, the range of usable fonts is greatly expanded since more than a single font encoding scheme is supported for a given locale. The process of purchasing and installing new fonts is significantly simplified since any font encoding scheme may be supported.

Abstract: Apparatus is disclosed for asynchronously controlling a pipeline. The control circuitry includes an alternating chain of control circuits and detection circuits. When a full control circuit precedes an empty control circuit in the chain, indicating that the data storage element corresponding to the full control circuit should transfer its data to the next storage element corresponding to the empty control circuit, the detection circuit generates a "move" signal. The "move" signal sets the preceding control circuit to empty and the following control circuit to full, thereby enabling movement of a data element from the preceding to the following stage. Because the control circuits are relatively simple and have predictable signal propagation times, the relative reactions of two adjacent control circuits to the common move signal can be tightly controlled. The control circuitry may control a counterflow pipeline, a forking pipeline, or a merging pipeline.

Abstract: A network interface circuit including an address translation unit and a flush check circuit, and a method for checking for an invalid address translation within of the address translation unit, are disclosed. A flush check circuit, in communication with the address translation unit, is implemented to determine, prior to loading an address translation into the internal memory, whether one of the plurality of entries already contains a virtual address utilized by the address translation. If so, an error has occurred with the flushing operations of the address translation unit because the address translation should have already been removed. In response, the flush check circuit signals logic to perform error handling techniques such as issuing an error signal, storing the invalid address translation unit, or transmitting the virtual address of the address translation without loading that address translation.

Abstract: A system is provided for rebooting a computer having a volatile memory device capable of storing operating information. The system reboots the computer using the operating information stored in the memory device if the memory device contains a valid copy of the operating information. The computer reboots the computer by reloading the operating information into the memory device if the memory device does not contain a valid copy of the operating information. The system determines whether the memory device contains a valid copy of the operating information by calculating a checksum for the operating information stored in the memory device and compares the checksum to a previously calculated checksum.

Abstract: A secure, trusted network management function embedded within a network interface device is provided. The network interface device connects a host computer to a network and contains a host bus interface, a network interface, and control logic. The network interface device incorporates a secure language processor, non-volatile memory, and a carrier sense circuit. The secure language processor executes a secure language program, and the non-volatile memory stores identification keys for remote devices and objects of value for network applications. If an application program is to be executed or accessed by the host computer, the secure language processor verifies that the object of value allows such execution or access. If a remote network device attempts to control the functionality of the network interface device, the secure language processor verifies that the remote network device has the authority to issue such a command.

Abstract: A partial store instruction and associated logic for storing selected bytes of a group of bytes in a register to a designated memory location. A mask in a separate register is used to enable particular bytes to be written, with only enabled bytes being written to the final location. The mask can be previously generated as a result of a comparison or other operation. The creation of the mask and the execution of a partial store instruction can also be used as a prefetch instruction, eliminating the need for a separate opcode for a prefetch.

Abstract: Three-dimensional compressed geometry is decompressed with a unit having an input FIFO receiving compressed data bits and outputting to an input block state machine and an input block, whose outputs are coupled to a barrel shifter unit. Input block output also is input to Huffman tables that output to the state machine. The state machine output also is coupled to a data path controller whose output is coupled to a tag decoder, and to a normal processor receiving output from the barrel shifter unit. The decompressor unit also includes a position/color processor that receives output from the barrel shifter unit. Outputs from the normal processor and position/color processor are multiplexed to a format converter. For instructions in the data stream that generate output to the format converter, the decompression unit generates a tag sent to the tag decoder in parallel with bits for normals that are sent to the format converter.

Abstract: A media server system and method for reducing the probability of data starvation or underflow in a media server system. The media server system preferably comprises a video server computer system which stores a plurality of encoded data streams, wherein the computer system is coupled through a SCSI (Small Computer Systems Interface) bus to one or more MPEG decoder blocks. The media server system thus utilizes a single control channel for multiple video channels. The present invention operates to fill the FIFO buffer of a channel to a higher level during startup, thus reducing the probability of data underflow. In one embodiment, the host computer or server begins data transmission prior to sending the "play" function or play command in order to pre-fill or pre-load the buffer. In another embodiment where the host server is not configured to pre-load the buffer prior to issuing the play command, the MPEG decoder block disables the FIFO buffer when the play command is received.

Abstract: A software package is installed to multiple target systems in a client/server distributed processing system. The software package is installed on program files of the server. A target list of clients served by the server is established, and the software package is installed on program files of each client in the target list. In one embodiment, the software package contains installation options for each client in the target list, and the target list establishing operation analyzes each client to determine what, if any, installation options are to be installed on the client and constructs a target list of clients and installation options for each client as determined by the analysis. In another embodiment, the software package contains additional software packages for each client on the target list and the target list establishing operation analyzes each client to determine if one or more client-specific packages are to be installed on the client and what are the to-be-installed, client-specific packages.