Abstract: In a computer system that utilizes write or read barriers to perform a garbage collection function, instruction execution logic avoids unnecessary calls to the write or read barrier procedure. Each object's header includes a State flag. Each object reference also includes a State flag. Each time an instruction that is the subject of a write or read barrier (e.g., a object reference write instruction) is executed, the State flag of the object reference being processed is inspected by the instruction execution logic. If the State flag in the object reference is set, the write or read barrier procedure is not invoked, because the target object has already been processed by a previous call to the write or read barrier procedure. Otherwise the write or read barrier procedure is invoked. The write or read barrier procedure first checks the State flag in the target object's header. If it is set, the State flag in the target object reference is set and then the procedure exits.

Abstract: A computer housing or electronic apparatus frame (10) includes a compartment (12) that provides space for mounting a fan assembly (14) or similar component. The fan assembly (14) is mounted on a fan tray support (16), which is removably mountable within the computer housing (10) by means of the fan tray mounts (18). Fan tray mounts (18) are oriented facing one another so that side rails (22) of fan tray (16) are slidably received by the fan tray mounts (18). The fan tray mounts (18) further includes an elongated guide channel (31) that extends the length of the fan tray mount and is formed in the inside face (30) thereof. The fan tray mounts (18) also include a first, outwardly projecting stop (52) that is positioned inwardly from end wall (38) and a second, outwardly-projecting, resiliently-deflectable stop and latch lever (54) provided adjacent end wall (36).

Abstract: A network management system allows a user to generate a customized event request for network accessible devices. In response to a user request the system displays a list of devices, and a list of predefined event requests. In response to user customization commands the system generates customized event requests by associating various ones of the displayed devices with various ones of the displayed predefined event requests. At most one predefined event request is associated with each device. The network management system periodically sends the customized event requests to the devices with which they have been associated, and receives response messages from those devices. A display or report may be generated showing the status of the responding devices, using the information in the received response messages. A predefined event request may be formed by storing one or more variable/threshold pairs in a predefined event request data structure.

Abstract: A dual instruction set processor decodes and executes code received from a network and code supplied from a local memory. Thus, the dual instruction set processor is capable of executing instructions in two different instructions sets from two different sources. The dual instruction set processor includes a computer platform independent instruction decoder, another decoder, and an execution unit that executes decoded instructions from both of the decoders. A computer system with the foregoing described dual instruction set processor, a local memory, and a communication interface device, such as a modem, for connection to a network, such as the Internet or an Intranet, can be optimized to execute, for example, JAVA code, in example of one set of computer platform independent instructions, from the network, and to execute non-JAVA code stored locally, or on the network but in a trusted environment or an authorized environment.

Abstract: Apparatus, methods, and computer program products are disclosed to simplify a computer user's navigation through a distributed information space. The invention provides the computer user with information identifying the server that provides access to data (or to services) of interest to the user.

Abstract: The present invention provides a hybrid Non-Uniform Memory Architecture (NUMA) and Cache-Only Memory Architecture (COMA) caching architecture together with a cache-coherent protocol for a computer system having a plurality of sub-systems coupled to each other via a system interconnect. In one implementation, each sub-system includes at least one processor, a page-oriented COMA cache and a line-oriented hybrid NUMA/COMA cache. Such a hybrid system provides flexibility and efficiency in caching both large and small, and/or sparse and packed data structures. Each sub-system is able to independently store data in COMA mode or in NUMA mode. When caching in COMA mode, a sub-system allocates a page of memory space and then stores the data within the allocated page in its COMA cache. Depending on the implementation, while caching in COMA mode, the sub-system may also store the same data in its hybrid cache for faster access.

Abstract: A method and apparatus for making flow information available for binary manipulation tasks are disclosed. Flow information is generated and saved either by a compiler or by a flow information generator. A compiler generates the flow information directly from a source file while the compiler is compiling the source file into an executable file. A flow information generator generates the flow information from an executable file in a manner similar to a compiler. Further, the flow information generator groups the executable file into units of text and traces the units to produce the flow information. The binary information thus retrieved is saved and embedded either in a text or a header of the executable file or placed in a file separate from the executable file. The flow information may be used in binary manipulations including binary translations, binary-to-binary optimizations, program tracing, and program debugging.

Abstract: A method of managing a linked-list data structure is disclosed. The linked-list data structure has a number of elements, each of which includes a data item and a pointer to a sequentially following element. The method allows the modification of the linked-list data structure, either by the insertion or removal of element therefrom, while permitting a concurrent and unsynchronized traversal operations with respect to the linked-list data structure. Specifically, the method requires that the pointers of elements within the linked-list data structure be modified using an atomic operation to reflect any modifications made to the linked-list data structure. The utilization of atomic operations to update the pointers ensures that the unsynchronized traversal operations examine a valid data path.

Abstract: Methods, systems, and software for installing and operating selected software applications on a client computer that is in communication with a server computer on a computer network is described. In one aspect, a method for installing and operating a selected software application on a client computer that is in communication with a server computer across a computer network. In one embodiment, browser software is provided on the client computer that includes a browser user interface and is effective to identify and download selected software applications from the server onto the client computer for execution thereby. A data transfer communication link is established between the client and server computers across the network, a desired software application is selected using the browser, and the desired software application is transmitted across the network from the server to the client.

Abstract: A system for controlling a device using a computer coupled to the device through a communication medium. The device contains an program code capable of generating control signals used by the device. A message is broadcast from the device across the communication medium indicating the existence of the device on the communication medium. The computer requests transmission of the device program code across the communication medium. The device then transmits the program code from the device to the computer. The program code is executed by the computer to generate control signals for controlling the device.

Abstract: A system for managing asset information pertaining to a network. A network information database may both provide a snapshot of the current state of the network and also track changes in configuration over time. Queries to the database concerning changes in network configuration may be readily generated.

Abstract: The present invention provides an improved method and apparatus for generating executable computer code for an application program written in C++ source code. In typical prior art systems, application program source code that has not itself been modified must still generally be recompiled in the event that object-oriented class definitions used by the application program and contained in separate header files have been modified. The methods and apparatus of the present invention reduce the need for such recompilation, by using procedural interfaces to implement object-oriented interfaces at the compiled code level. Thus, in accordance with the present invention, compiled header file code is generated that includes accessors for accessing object instances of the class definitions, each of the accessors being a procedure operative to access the object instances of the corresponding class definition.

Abstract: A preferred embodiment of the present invention includes a method and apparatus for routing an IP packets in a network of client systems. The router forwards IP packets between the client systems and the server systems. More specifically, the router can be pre-configured to include one or more "routes." Each route is a mapping between an IP address and a client system. The router may also learn route from other routers and by analysis of IP packets. Preferably, the routes known by the router are included in a route table. The router also monitors DHCP assignment of IP addresses to client systems within the network. When the DHCP assignment of an IP address is detected, the router creates a new route that associates the newly assigned IP address and the corresponding client system. The new route is marked so that it may only be overwritten by a subsequent DHCP assignment.

Abstract: A method for allowing a RAM array within an SRAM to be tested via scan ATPG is disclosed. A first clocked flip-flop has a data input latched high, a scan-in input latched high, a clock input coupled to a signal source generating a periodic waveform, a scan-enable input coupled to a scan enable signal, and an output. The first flip-flop inverts the data input at the output when the scan enable signal is low, and places the scan-in input signal at the output when the scan enable signal is high. A second clocked flip-flop has a data input coupled to the output of the first flip-flop, a scan-in input latched high, a clock input coupled to the signal source, a scan enable input coupled to the scan enable signal, and an output. The second flip-flop inverts the data input at the output when the scan enable signal is low, and places the scan-in input signal at the output when the scan enable signal is high.

Abstract: A computer system includes multiple local buses to which processors and other devices may be connected. A repeater is coupled to each of the local buses. Additionally, a top level repeater is coupled to each of the repeaters. The repeaters transmit transactions from the corresponding local buses to the top repeater. The top repeater, based upon the local or global nature of the transaction, transmits the transaction to one or more of the repeaters. The repeaters receiving the transaction then transmit the transaction upon the local buses attached thereto. If the transaction is a local transaction, the top repeater transmits the transaction to those repeaters which are configured into a local domain with the repeater which detected the initial transaction. The local domain comprises one or more repeaters which are logically interconnected. The local buses attached thereto logically form one SMP bus to which devices may be attached. Alternatively, the transaction may be a global transaction.

Abstract: Disclosed is a low threshold asymmetric MOS device having a pocket region with a graded concentration profile. The pocket region includes a relatively high dopant atom concentration (of the same conductivity type as the bulk region) abutting either the device's source or its drain along the side of the source or drain that faces the device's channel region. The pocket region's graded concentration profile provides a lower dopant concentration near the substrate surface and an increasing dopant concentration below that surface. This provides a relatively low resistance conduction path through the pocket region, while allowing the device's threshold voltage to be somewhat higher at the pocket region. The asymmetric device can also include a counter dopant region located beneath its substrate surface. This forces current to flow in the substrate but just above the region of high counter dopant concentration, where the resistance is relatively low.

Abstract: A system, method, and apparatus is disclosed for executing an architecture-independent binary program on a computer. An object file is read, and architecture-independent object code is extracted from the object file. Dynamic dependency information is also extracted from the object file. The dependency information is provided to an interpreter, which is invoked to execute the object code. The object file is preferably in an architecture-neutral format, preferably the ELF format defined as the standard binary interface that is used by application programs on operating systems that comply with the UNIX System V Interface Definition.

Abstract: A system and process for efficiently determining absolute addresses for an intermediate code model of an address space are described. A processor interfaces to a main memory comprising a plurality of addressable locations. Each such addressable location is referenced by an absolute address having a maximum size directly proportional to the total number of the addressable locations in the main memory. The absolute addresses form the address space. Source code is supplied specifying program routines which each include at least one reference to an absolute address within the address space. A translator interfaces with the main memory and the storage device. Object code is generated from the source code program routines. Each such absolute address reference in the source code program routines is instantiated with a code sequence for referencing a subset of the address space.

Abstract: A single phase edge-triggered dual-rail dynamic flip-flop circuit for use with dynamic logic gates includes an input stage, precharge stage and buffer. The input stage is coupled to receive a data-input signal and a clock signal. During the precharge phase, the input stage provides an output signal that is the complement of the data input signal. When the data input signal is provided by a dynamic logic gate, the input stage output signal is precharged to a logic high level. During the evaluation phase, the input stage generates an output signal that either remains at a logic high level or else transitions from high-to-low. The precharge stage receives the output signal from the input stage and the clock signal. During the precharge phase, the precharge stage generates a logic high level output signal independently of the signal received from the input stage.

Abstract: Circuits and methods for eliminating hold time violations are disclosed. A DE-type flip-flop latches a data input signal on a data input terminal a fraction of a clock period before a triggering edge of the clock signal. The DE-type flip-flop provides a data output signal for a full clock period beginning after the triggering edge of the clock signal. The DE-type flip-flop includes a latch having its data output terminal coupled to the data input terminal of a flip-flop. The flip-flop clock input pin and the latch enable terminal of the latch are connected to a clock line. The DE-type flip-flop used in place of a standard flip-flop, in which a hold time violation occurs, eliminates the hold time violation.