Abstract: A method and apparatus for ordering blocks of code by a compiler. The compiler generates a conflict graph in accordance with the blocks of a computer program being compiled. Once the conflict graph is generated, a preferred embodiment of the present invention finds maximum weight independent set (MWS) of nodes in the conflict graph. By definition, the nodes in the MWS have no flow control conflicts between them. The compiler then generates an object program having blocks ordered in accordance with the maximum weight independent set.

Abstract: Global address and data routers interconnect individual system units each having its own processors, memory, and I/O. A domain filter coupled to the routers dynamically defines groups of system units as domains and clusters of domains which have both software and hardware isolation from each other. Clusters can share dynamically definable ranges of memory with each other. The domain filter has software-loadable registers on the system units and in the global routers to set the parameters of the domains and clusters. The registers label individual inter-system transactions on the routers as invalid for system units not in the same domain or cluster as the originating unit.

Abstract: Circuits and methods of suppressing noise on a signal line are disclosed. A noise suppression pull-down circuit is coupled to a signal line which couples the output element of a first logic element to the input terminal of a second logic element. When the first logic element drives a logic low onto the signal line, the noise suppression pull-down circuit is activated to provide a weak pull-down on the signal line. When the first logic element drives a logic high onto the signal line, the noise suppression pull-down circuit is deactivated to prevent interference with the first logic element.

Abstract: The present invention provides a user control mechanism for selectively retaining for display a document obtained from a network. The user control is located as an icon or symbol in the browser interface for ease of use. Subsequent documents which are downloaded from the network are displayed in a separate window of the display in the computing system, and these subsequent windows are also provided with the same user control mechanism. In particular, the user can selectively create a second browser display page by following a link contained in the first browser display page, without overwriting the contents of the first browser display page.

Abstract: A method and apparatus for switching between threads of a program in response to a long-latency event. In one embodiment, the long-latency events are load or store operations which trigger a thread switch if there is a miss in the level 2 cache. In addition to providing separate groups of registers for multiple threads, a group of program address registers pointing to different threads are provided. A switching mechanism switches between the program address registers in response to the long-latency events.

Abstract: Methods and apparatus for dynamically deoptimizing a frame in a control stack during the execution of a computer program are disclosed. The described methods are particularly suitable for use in computer systems that are arranged to execute both interpreted and compiled byte codes. According to one aspect of the present invention, a computer-implemented method for deoptimizing a compiled method includes creating a data structure. The data structure, which is separate from the control stack, is arranged to store information relating to the compiled method. A reference indicator, such as a pointer, is created to associate the data structure with the frame. The method, which is compiled to a first state of optimization, is then deoptimized to a second state of optimization, and the method in the first state of optimization may be discarded, thereby deoptimizing the frame.

Abstract: In a computer system comprising a CPU, a cache memory and a main memory wherein the cache memory is virtually addressed, and some of the virtual addresses are alias address to each other, a cache memory controller comprising a cache control logic, a cache tag array, a memory management unit, and an alias detection logic is provided. The cache control logic skips flushing of a cache line if the cache line is corresponding to a memory block in a non-cacheable physical memory page, thereby avoiding unnecessary flushes and allowing the CPU to update the cache memory and the main memory using an improved write through and no write allocate approach that reduces cache flushes.

Abstract: A system that decapsulates an integrated circuit package while the package is mounted to a printed circuit board. The system includes a tray that supports a printed circuit board which has at least one integrated circuit package mounted to the board. Mounted to the tray is a clamp which clamps an injection head to the top of the package. The injection head is coupled to a source of decapsulation fluid which is sprayed onto the package. The decapsulation fluid is circulated across the package to remove the package material and expose the underlying integrated circuit. The injection head has a gasket that is pressed onto the package to prevent the fluid from leaking onto the printed circuit board. After the plastic is decapsulated the head can be removed from the package so that the integrated circuit can be tested while the circuit is connected to the printed circuit board.

Abstract: A flip-flop circuit for use with logic gates includes a dynamic input stage and a static output stage. The flip-flop receives a single phase which defines a precharge phase and an evaluation phase. The dynamic input stage has a NMOS logic block coupled to receive one or more data signals. The dynamic input stage output signal is precharged to a logic high level during the precharge phase. During the evaluation phase, the NMOS logic block of the dynamic input stage causes the dynamic input stage to generate an output signal that either remains at a logic high level or else transitions from high-to-low by performing a logic operation of the data signals. The static output stage receives the output signal from the dynamic input stage and the clock signal. During the precharge phase, the static output stage maintains the flip-flop output signal logic at the logic level of the previous evaluation phase independently of the signal received from the dynamic input stage.

Abstract: A high-performance band combine function to transform a source image of n bands to a destination image of m bands. A source image vector is multiplied with a transformation matrix having n+1 columns and m rows. The values in the transformation matrix may be user-selected. The product of the source image and the transformation matrix is a destination image vector. The destination image vector may be displayed on a computer monitor. To perform the function in a digital system, the pixels of the source image are converted to a partitioned format. The source image is multiplied with the transformation matrix values using partitioned arithmetic. In the digital system, a plurality of partitioned arithmetic operations may be performed in parallel.

Abstract: An interface circuit, coupled between a first circuitry that is synchronous to a first clock (sclk) and a second circuitry that is synchronous to a second clock (mclk), for transferring data between the first and second circuitry and achieving a fast turn-around time between a data request from the mclk domain circuitry and a bus request in the sclk domain. A first FIFO buffer for transferring data from the first circuitry to the second circuitry is provided. Logic associated with the first FIFO to synchronize reads and writes to the first FIFO is also provided. A read Bus Request Enable Generator provides a read bus request enable signal to the first circuitry, and an At.sub.-- least.sub.-- x.sub.-- words.sub.-- filled Flag Generator provides a plurality of flags, which indicate degrees of fullness of the first FIFO buffer to the second circuitry. A second FIFO buffer transfers data from the second circuitry to the first circuitry.

Abstract: The integer execution unit (IEU) of a central processing unit (CPU) is provided with a graphics status register (GSR) for storing a graphics data scaling factor and a graphics data alignment address offset. Additionally, the CPU is provided with a graphics execution unit (GRU) for executing a number of graphics operations in accordance to the graphics data scaling factor and alignment address offset, the graphics data having a number of graphics data formats. In one embodiment, the GRU is also used to execute a number of graphics data addition, subtraction, rounding, expansion, merge, alignment, multiplication, logical, compare, and pixel distance operations. The graphics data operations are categorized into a first and a second category, and the GRU concurrently executes one graphics operations from each category.

Abstract: A non-interruptive, context-based help system and method for use in a WorldWideWeb based environment includes links to help software that, when activated, tracks the user's position and simultaneously displays a miniaturized depiction of the active Web page in a child window with help information appropriate to the active Web page. The user may select portions of the miniaturized depiction, causing the help software to display help information specific to the selected portion of the page. Preferably, the help software is a Java.TM. application or applet.

Abstract: Apparatus, methods, systems and computer program products are disclosed to provide improved optimizations of single-basic-block-loops. These optimizations include improved scheduling of blocking instructions for pipelined computers and improved scheduling and allocation of resources (such as registers) that cannot be spilled to memory. Scheduling of blocking instructions is improved by pre-allocating space in the scheduling reservation table. Improved scheduling and allocation of non-spillable resources results from converting the resource constraint into a data dependency constraint.

Abstract: A data cache unit associated with a processor, the data cache unit including a multi-ported non-blocking cache receiving a data access request from a lower level device in the processor. A memory scheduling window includes at least one row of entries, wherein each entry includes an address field holding an address of the access request. A conflict map field within at least some of the entries is coupled to a conflict checking unit. The conflict checking unit responds to the address fields by setting bits in the conflict map fields to indicate intra-row conflicts between entries. A picker coupled to the memory scheduling window responds to the conflict map fields so as to identify groups of non-conflicting entries to launch in parallel at the multi-ported non-blocking cache.

Abstract: A system and method for displaying still video images related to video content in an interactive broadcast television system. The system and method of the present invention may also be used for simulating an Internet home page on an interactive television system. The present invention thus supports hyperlinked web-like navigational capabilities in an interactive television system. According to the method of the present invention, the video delivery system provides or broadcasts one or more audio/video channels each comprising video content and also provides or broadcasts at least one still image channel comprising a plurality of still video images, preferably MPEG-2 compressed still images. The user or viewer can select options displayed on the television screen to view desired information.

Abstract: A method and apparatus for operating a local server computer of a client-server network includes a technique to receive a request from a client computer of the client-server network. A determination is made whether the request requires dynamically generated information from a servlet object of the client-server network. If so, a specified servlet object corresponding to the request may be uploaded from a remote server computer of the client-server network. The specified servlet object is then executed to obtain dynamically generated information corresponding to the request.

Abstract: A file system for use in a network computer system has a server file system in the server, which contains at least some file elements to be selectively accessed by the client. An overlay file system is assigned to the client within the server, and contains at least some file elements that have corresponding file elements in the server file system. The overlay file system is configured to provide an overlay file system element to the client when the file element exists in the overlay file system, and to allow access to a server file element when a corresponding file elements does not exist in the overlay file system. Through the use of such file system, a network file system can be configured to allow the client to write to it, with the appearance to the client that it is writing directly to the server file system.

Abstract: The present invention solves the problems associated with the prior art by decoupling the issuing of instructions from their dispatch into their respective pipeline. This permits the determination of whether a particular instruction can safely be issued from an instruction queue to the next stage of the pipeline by providing such information at a point early in the machine cycle.

Abstract: Each character in a message is segregated into a range depending on the value of the character and encoded based on the range of the character. The encoding techniques may include removing all but the lowest byte, removing all but the lowest byte and masking one or more bits, base 64 encoding, base 64 encoding certain bits, and subtracting prior to base 64 encoding certain bits. To certain encoded characters is added a shift character, which can be used to determine how to decode the character. Multiple characters in the same range may be encoded and placed between a shift lock character and a shift unlock character, with the shift lock character used to determine how to decode the encoded characters. The encoded characters may be decoded using the encoded character, and the absence or presence of any shift, shift lock or shift unlock characters.