Abstract: In a charge pump the noise due to switching transients on the input pulse lines is kept to extremely low levels by translating input up/down pulses into small signal differential pulses which swing a differential pair of transistors by a small amount. This is done with level converters. The differential pair is kept in a saturation region, so that a large swing is not needed from the level converters and channel creation/destruction noise is avoided in addition to the noise reduction due to smaller swings. To avoid inherent offsets which might require a nonzero delta time width difference in the input pulses to produce a zero delta current, identical differential structures are used at the inputs for the two input pulse signals.

Abstract: A multi-layer distributed network element for relaying packets according to known routing protocols. A distributed architecture of multiple subsystems delivers routing at wire-speed performance across subnetworks. Each subsystem includes a forwarding memory and an associated memory and is configured to identify unicast and multicast packets for routing purposes, modify the packets in hardware, including replace VLAN information, and forward the packets to the next hop. The routing decisions are made in the inbound subsystem, and packets are forwarded, if necessary given the network topology, through a separate outbound subsystem.

Abstract: One embodiment of the present invention presents a method and apparatus for efficiently performing garbage collection on objects defined within an object-oriented programming system. Garbage collection typically involves following pointers to determine which objects are presently being referenced so that other objects, that are not being referenced, can be removed. To this end, the present invention maintains a bitmap for each object that indicates which variables in the object are pointer variables and which variables are non-pointer variables. A garbage collection process examines the bitmap, and on the basis of the pattern contained in the bitmap jumps to a particular routine that is tailored to garbage collect the particular pattern of pointer and non-pointer values in the object. Note that the system includes a routine tailored for each possible bitmap pattern.

Abstract: A method, apparatus, and computer program product for selecting and reviewing a distributed object installed on a distributed object system. A method of the invention includes generating a library of components corresponding to distributed objects on the distributed object system, which includes one component corresponding to the distributed object. Each of the components of the library includes information describing the distributed object to which the particular component corresponds. The contents of the library are displayed using a catalog interface device. The library is browsed using the catalog interface device to identify the component corresponding to the distributed object which is then selected. At least a portion of the information describing the distributed object is displayed.

Abstract: An apparatus for processing a write miss signal from a copy-back data cache includes a load-store unit with an allocating load buffer, a non-allocating store buffer, and a priority control circuit to generate write-after-read hazards and read-after-write hazards to preserve the processing priority of entries within the allocating load buffer and the non-allocating store buffer. A prefetch circuit enqueues a prefetch command in the allocating load buffer and a store command in the non-allocating store buffer upon a write miss to the copy-back data cache. Thus, the priority control circuit forces a write-after-read hazard on the store command in the non-allocating store buffer. As a result, the prefetch command in the allocating load buffer secures an allocated line in the copy-back data cache, allowing the store command of the non-allocating store buffer to write data to the allocated line.

Abstract: A system clock generator for a computer system to efficiently transfer data from a source subsystem to a destination subsystem of the computer system. The system clock generator generates a globally synchronized clock signal for the source subsystem and the destination subsystem. The source subsystem includes a clock generator for generating a source clk (SRC.sub.-- CLK) signal and a source-synchronous clock (SRC.sub.-- SYN.sub.-- CLK) signal for the source subsystem and destination subsystem, respectively. The SRC.sub.-- SYN.sub.-- CLK signal is generated whenever data is transferred from the source subsystem to the destination subsystem. Upon receiving the data and SRC.sub.-- SYN.sub.-- CLK signal from the source subsystem, the data is synchronized at the destination subsystem using the SRC.sub.-- SYN.sub.-- CLK signal. Since the source and destination subsystems are synchronized by the system clock signal, an incoming data stream can be synchronized within one system clock cycle.

Abstract: A cache structure for a microprocessor which provides set-prediction information for a separate, second-level cache, and a method for improving cache accessing, are provided. In the event of a first-level cache miss, the second-level set-prediction information is used to select the set in an N-way off-chip set-associative cache. This allows a set-associative structure to be used in a second-level cache (on or off chip) without requiring a large number of traces and/or pins. Since set-prediction is used, the subsequent access time for a comparison to determine that the correct set was predicted is not in the critical timing path unless there is a mis-prediction or a miss in the second-level cache. Also, a cache memory can be partitioned into M sets, with M being chosen so that the set size is less than or equal to the page size, allowing a cache access before a TLB translation is done, further speeding the access.

Abstract: The present invention is directed to a coaxial waveguide applicator for an electromagnetic wave-activated sorption system which comprises at least one sorber having a metallic tubular housing defining an outer conductor and first and second ends which are sealed to define an enclosure within the outer conductor; a sorbate/sorbent compound located within the enclosure; the sorber including a port through which a sorbate may be communicated into or out of the enclosure; a metallic inner conductor extending into the outer conductor and parallel to the longitudinal axis of the sorber; an electromagnetic wave generator; and a waveguide for coupling electromagnetic waves generated by the electromagnetic wave generator to the inner and outer conductors; wherein electromagnetic waves transmitted by the electromagnetic wave generator are propagated through the enclosure by the inner and outer conductors to desorb the sorbate from the sorbate/sorbent compound.

Abstract: A single phase edge-triggered staticized dynamic flip-flop circuit for use with dynamic logic gates includes a dynamic input stage and a static output stage. The dynamic input stage is coupled to receive a data signal and a clock signal. During the precharge phase, the dynamic input stage provides an output signal that is the complement of the data signal. The dynamic input stage output signal is precharged to a logic high level during the precharge phase. During the evaluation phase, the dynamic input stage generates an output signal that either remains at a logic high level or else transitions from high-to-low, complementing the logic level of the data signal. The static output stage receives the output signal from the dynamic input stage and the clock signal. During the precharge phase, the static output stage maintains the flip-flop output signal logic at the logic level of the previous evaluation phase independently of the signal received from the dynamic input stage.

Abstract: The present invention is directed to checking and reducing an intermediate signal arising from a manipulation of 16-bit signed data signals without using conditional branches, thereby improving instruction processing in a superscalar pipelined processor or an arithmetic unit that can execute several arithmetic operations concurrently. In the preferred embodiment of the present invention, the data signals are represented as signed 16-bit binary values in a two's compliment format. An intermediate register is used to hold the intermediate signal which is greater than 16-bits in width to allow for the proper checking of an overflow condition. It is presently contemplated that the present invention include using a processor operating under program control. The program determines whether the intermediate signal is in a positive or negative overflow state.

Abstract: The present invention solves the problems associated with the prior art by decoupling the issuing of instructions from their dispatch into their respective pipeline. This permits the determination of whether a particular instruction can safely be issued from an instruction queue to the next stage of the pipeline by providing such information at a point early in the machine cycle. In a multistage pipeline, a first stage is bypassed to provide instructions to a second stage regardless of the ability of the first stage to store the instruction from the instruction issuing unit.

Abstract: The present invention provides a method and system in computer systems for converting an original image into another image having fewer colors than the original image. This method and system attempt to preserve the contrast of the original image. As a result, this method and system are particularly well-suited for converting images that are relatively small in size. A computer system in which the present invention operates includes a computer connected to a display device and a secondary storage device. An image converter is stored in the secondary storage device for execution by the computer. In operation, the computer receives an original image to be displayed on the display device. The image converter converts the original image into another image having fewer colors than the original image. Lastly, the computer displays the converted image on the display device. In order to convert the original image, the image converter determines which pixels in the original image are opaque in the converted image.

Abstract: A lighting unit which exhibits improved handling of incoming color values corresponding to a polygon. The lighting unit includes an input buffer for storing a plurality of color values, a mode register including a color mode field specifying whether the plurality of color values corresponds to the front or back side of the polygon. Furthermore, the lighting unit includes a register file for storing color information. The register file includes a first and second plurality of registers for storing front and back side color information, respectively. Still further, the lighting unit includes input/output logic configured to perform a transfer color instruction, which first comprises accessing the mode register to obtain a value of the color mode field, and then transferring the plurality of color values from the input buffer to one or more registers within the register file.

Abstract: A network browser system facilitates browsing of resources in a network, each of the resources having a respective network address. The network browser system includes a browsing control list and a browsing computer. The browsing control list includes at least one network specifier entry that identifies at least a portion of the network, the portion having associated therewith a range of network addresses. The browsing computer is responsive to a browsing request from an operator to initiate a browsing operation in connection with the network. During the browsing operation, the browsing computer generates, from the network specifier entry in the browsing control list, a plurality of browsing request messages that are associated with respective ones of the network addresses in the network address range, and transmits the browsing request messages over the network.

Abstract: A portable emergency locator device includes a global positioning system (GPS) receiver generating location data and a wireless telephone transceiver for transmitting the location data as digital data to a called station during a two-way voice conversation via a wireless telephone network (cellular, PCS, or satellite). The emergency locator device can be implemented as a conventional wireless telephone having interfaces for receiving the location data from an external GPS receiver and vehicle status data from external vehicle control systems. The data received from the interfaces is stored in an internal memory for transmission to the called station in response to an emergency event trigger.

Abstract: Apparatus, methods, systems, and computer program products are disclosed that use a link to access nodes in a generational garbage collected heap. The creation area of the heap is associated with a validation variable that is dependent on the number of scavenge operations performed on the creation area. The link comprises the value of the validation variable when the node was allocated and the index of the created node within the creation area. When the node is copied from the creation area an entry is made in a link-to-pointer translation table. Accesses to the node using the link succeed regardless of whether the node is in the creation area. Thus, not all references to the node need to be updated when the node is copied from the creation area allowing the copying process to be interrupted when resolving links to the copied node.

Abstract: Extended trinary signal apparatus includes window comparator logic having first and second inputs for first and second trinary input signals, wherein each the trinary input signal can be a high, low or mid state, and an output for outputting signals dependent on the states of the first and second trinary input signals. A switch, which is connected to one of the first and second inputs, can be selectively activated in one phase to set the one of the first and second inputs to a state other than the mid state and can be inactive in another phase. Control logic is responsive to output signals from the window comparator output during the one and the other phase to provide extended trinary decoding of the trinary input signals.

Abstract: For controlling access to a system resource in a processing system, reprogrammable logic located between a bus and the resource is programmed in a first mode to permit access to the resource and is programmed in a second mode to at least restrict access to said resource via the bus. The resource can be a critical area of storage holding or identifying critical operational parameters or critical operational software relating to the processing system. The reprogrammable logic is preferably implemented using a field programmable gate array.