Abstract: A method for generating code for an object-oriented processor is disclosed. An instruction table is initialized to include a plurality of instructions for an object-oriented processor, each of the plurality of instructions having a set of operands and an operand type for each of the set of operands. In addition, a weighting table is initialized to include a set of the plurality of instructions and a weight for each of the set of the plurality of instructions, the weight indicating frequency of generation for a particular instruction. A class hierarchy is created, the class hierarchy having a plurality of classes stored in a tree data structure, each of the plurality of classes having a set of fields and a set of methods, each of the plurality of classes, each of the set of fields, and each of the set of methods having object-oriented properties. Within the class hierarchy, a set of objects is randomly generated for each of the plurality of classes.

Abstract: Method, system and article of manufacture for creating hierarchical folder components for use with in holding other object oriented based components, including other folder components, and component assemblies. Each hierarchical folder is provided with an editor that pops up upon its instantiation and permits a user to edit the folder component name as well as the number and type of ports assigned to the folder component.

Abstract: On-chip delivery of data from an on-chip or off-chip cache is separated into two buses. A fast fill bus provides data to latency critical caches without ECC error detection and correction. A slow fill bus provides the data to latency insensitive caches with ECC error detection and correction. Because the latency critical caches receive the data without error detection, they receive the data at least one clock cycle before the latency insensitive caches, thereby enhancing performance if there is no ECC error. If an ECC error is detected, a software trap is executed which flushes the external cache and the latency sensitive caches that received the data before the trap was generated. If the error is correctable, ECC circuitry corrects the error and rewrites the corrected data back to the external cache. If the error is not correctable, the data is read from main memory to the external cache.

Abstract: A phased lock loop (PLL) clock circuit generates a clock signal at 1x the desired clock frequency while maintaining substantially a 50% duty cycle. A first loop provides a feedback signal to maintain clock frequency, while a second loop provides a feedback signal and controls duty cycle. Two clock signals from a ring oscillator are fed to a level shifter, where each clock signal triggers a respective rising or trailing edge of the output clock signal. The level shifter is provided with a delay for controlling timing of the trailing edge of the output clock signal. The output clock signal is fed to a equi-current buffer where a charge pump, driven by the output clock signal, charges and discharges a capacitor in proportion to the duty cycle of the output clock signal, producing a feedback control voltage. The feedback control voltage is applied to the delay of the level shifter to maintain a substantially 50% duty cycle.

Abstract: An enclosure is assembled from metal-plated rigid structural foam plastic components to house in minimal space in many hard disk drives. Major components, including the power supply, plug directly to a motherboard at the rear of the enclosure, eliminating internal cables. The parts fit together in snap-in fashion in such manner that the back will not close if parts are not installed properly. For ventilation, slots are formed in the sides and a central partition which permit air from fans on one side to flow laterally across all the disk drives and then out through slots in the opposite side. A side facing door permits easy access to all drives simultaneously for service and upgrade.

Abstract: According to a presently preferred embodiment of the present invention, a method for processing a incoming signal comprising the steps of selecting a first set of bits of digital information from a first signal, selecting a second set of bits of digital information from a second signal, reading the first set of bits of signal information into a first contiguous memory space to form a first word, and then reading the second set of bits of signal information into a second contiguous memory space to forming a second word, performing a first EXCLUSIVE OR operation on the first word with the second word, performing a first logical AND operation on the first word with a mask, performing a second logical AND operation of said second word with a mask, performing a first addition operation of the results of the first logical AND operation with the results of the second logical AND operation, performing a third logical AND operation on the results of the first EXCLUSIVE OR operation with a mask word, and then performin

Abstract: In a sample-and-hold circuit, an input is tracked at an output during a tracking period and the input is held during an holding period, the tracking period and holding period defined by a clock signal input to the sample-and-hold circuit, wherein the output is a differential output having a positive output node and a negative output node with the output signal represented by a voltage difference from the negative output node to the positive output node. During the tracking period, an equalizing transistor between the output nodes is turned on to bring the output to a common mode level for the output. During the holding period, the equalizing transistor is turned off and a regenerative circuit drives the output nodes apart, thus amplifying the input signal.

Abstract: A parallel processor which is capable of partitioned multiplication and partitioned addition operations convolves multiple pixels in parallel. The parallel processor includes a load and store pipeline of a load and store unit which retrieves data from and stores data to memory and one or more arithmetic processing pipelines of an arithmetic processing unit which aligns data and performs partitioned multiplication and partitioned addition operations. A patch of pixels from a source image are convolved substantially simultaneously in the arithmetic processing pipeline of the processor by execution of the partitioned multiplication and partitioned addition operations. At substantially the same time, a subsequent patch of pixels from the source image are read by the load and store unit of the processor.

Abstract: An apparatus for securing a conductor to a circuit board. The conductor is configured for being soldered to the circuit board through a first aperture in the board. The apparatus includes a conductor supporting portion having a second aperture therethrough. The conductor supporting portion is configured for coupling to the circuit board. The second aperture substantially aligns with the first aperture when the conductor supporting portion is coupled to the circuit board to permit the conductor to be inserted through both the first aperture and the second aperture. The apparatus includes a tab portion configured for coupling to the conductor supporting portion. A portion of the conductor is thus held substantially immobile between the conductor supporting portion and a first edge of the tab portion when the tab portion is coupled with the conductor supporting portion, thereby preventing the conductor from being broken at the portion of the conductor when the conductor is flexed.

Abstract: A configuration parameter value access system used in connection with a computer system performs an access operation in connection with a configuration parameter in response to a configuration parameter access request from an applications program. Each configuration parameter access request includes a parameter class identifier, a filename and a parameter identifier. The configuration parameter value access system includes a plurality of configuration file path class lists, each of which has at least one entry, each entry defining a storage subsystem path in the computer system's storage subsystem. A file identifier generator tests successive entries of the configuration file path class list identified by the parameter class identifier to determine whether the storage subsystem contains a file which has the filename provided in the configuration parameter access request along a path defined by an entry.

Abstract: A method which may be implemented in a library routine for performing an image transformation. First, a plurality of groups of bits are selected, with each group being from a different row and the rows being aligned in the same column in an image. Next, a logical operation is performed to set to zero all of the bits in the group except for the designated position of the column to be transformed. Finally, each of the groups or rows are compared to a template, and a single bit indicating the result of such comparison is stored in a result register.

Abstract: Apparatus, methods, systems, and computer program products are disclosed that generate a hash value for a node allocated from a generational garbage collected heap. The heap is associated with a global hash offset that is updated on every scavenge operation. This global hash offset is added to the address of the node to generate a hash offset. The hash offset is only generated upon a generate hash condition. The generate hash condition occurs when the hash value for the node is accessed or when the node is copied from the creation area. Thus, the invention generates hash values for nodes that require them while in the creation area of the heap. When the active nodes are copied from the creation area of the heap the hash value is generated as part of the copy process without additional memory accesses.

Abstract: A split transaction snooping bus protocol and architecture is provided for use in a system having one or many such buses. Circuit boards including CPU or other devices and/or distributed memory, data input/output buffers, queues including request tag queues, coherent input queues ("CIQ"), and address controller implementing address bus arbitration plug-into one or more split transaction snooping bus systems. All devices snoop on the address bus to learn whether an identified line is owned or shared, and an appropriate owned/shared signal is issued. Receipt of an ignore signal blocks CIQ loading of a transaction until the transaction is reloaded and ignore is deasserted. Ownership of a requested memory line transfers immediately at time of request. Asserted requests are queued such that state transactions on the address bus occur atomically logically without dependence upon the request. Subsequent requests for the same data are tagged to become the responsibility of the owner-requestor.

Abstract: A circuit and method for accelerating the division algorithm and square root operations relating to integers or floating-point numbers. Minimization of the number of gate delays per quotient digit generated is achieved through the use of triply-redundant representation of the partial remainder and a fully-overlapped quotient digit prediction scheme suitable for logic implementation. Moreover, faster quotient digit selection is achieved by prescaling the dividend and divisor.

Abstract: A computer implemented method and computer system for testing a target software product is presented. The method includes constructing a finite state machine in which portions of the target product are ascribed to states of the state machine. The state machine may correspond to a predetermined test case for the target software product. A number of state functions are provided, each of the state functions performing at least one verification on the target software product. The state functions also may include means for transitioning from one state to the next, for example, by a "next window" a "previous window" action if the target software program is a windows based program. The state functions may also verify that a current state in which the state machine exists is a correct state, may verify information that is supposed to have been written to a memory is written in fact to the memory, and may verify that the path to the information is correct.

Abstract: Disclosed is a process and apparatus for controlling a power shutdown of an electrical device. The operations for controlling a power shutdown include determining a value MAX indicating a maximum number of safe power-on transitions that could have been experienced by the electrical device prior to a specified date. In addition, a threshold value P indicating a number of permissible power-on transitions prior to the specified date is determined from the value MAX. A value N indicating a number of power-on transitions that have occurred prior to the specified date is then determined. The power shutdown is inhibited if the value N is greater than the threshold value P, and otherwise allowed.

Abstract: The invention creates a self-contained executable application. A compiler compiles an application including main source code and initialization code to generate a list of objects needed for execution of the application. A processing device executes the compiled application to cause the initialization code to load the listed objects as persistent objects into a single persistent store. The processing device then stabilizes the persistent store to create the self-contained executable application which appears to a user as a single executable file.

Abstract: A method and apparatus for providing hardware-assisted CPU access to a forwarding database is described. According to one aspect of the present invention, a switch fabric provides access to a forwarding database on behalf of a processor. The switch fabric includes a memory access interface configured to arbitrate access to a forwarding database memory. The switch fabric also includes a search engine coupled to the memory access interface and to multiple input ports. The search engine is configured to schedule and perform accesses to the forwarding database memory and to transfer forwarding decisions retrieved therefrom to the input ports. The switch fabric further includes command execution logic that is configured to interface with the processor for performing forwarding database accesses requested by the processor.

Abstract: A digital electronic circuit device comprises a plurality of circuit elements, a scan chain establishment element, and a unitary clock domain establishment element. The plurality of circuit elements define a plurality of clock domains, and circuit elements in each clock domain perform processing operations under control of a respective domain clock signal. The scan chain establishment element interconnects the circuit elements in a scan chain to facilitate loading and/or retrieval of a scan vector into and/or out of the digital circuit device. The unitary clock domain establishment element establishes a unitary clock domain for the circuit element when the scan chain establishment element is interconnecting the circuit elements in a scan chain.