Abstract: A diagnostic subsystem is used in a digital device in a digital computer system includes a diagnostic register, a device output control circuit and a diagnostic register reset circuit. The diagnostic register includes a plurality of stages each of which is associated with one of the types of transfers over the bus. Each stage is selectively conditionable by the digital computer system's processor. The device output control circuit controls transfers by the digital device over the bus. The device output control circuit enables the digital device, when it is to engage in a transfer, to transfer information correctly when the associated stage is set and to transfer information incorrectly when the stage has the set condition. For transfers in which the one device is to transmit information over the bus, the incorrectly transmitted information causes error checking circuitry in other devices in the system to generate error indications, which are provided to the processor.

Abstract: A multi-threaded processing system has a cache that is commonly accessible to each thread. The cache has a plurality of entries for storing items, each entry being identified by an entry number. The location in the cache of an item that includes a first key is determined by supplying the first key to a lockless-lookup engine which then provides a lookup output that is alternatively a lookup entry number or an indication that the item is not stored in the cache. The lookup entry number is alternatively a first or second entry number, wherein the first entry number points to a first entry in which the item is stored and the second entry number points to a second entry in which the item is not stored. If the lookup output is the lookup entry number, then it is verified that the lookup entry number is the first entry number.

Abstract: A non-inclusive multi-level cache memory system is optimized by removing a first cache content from a first cache, so as to provide cache space in the first cache. In response to a cache miss in the first and second caches, the removed first cache content is stored in a second cache. All cache contents that are stored in the second cache are limited to have read-only attributes so that if any copies of the cache contents in the second cache exist in the cache memory system, a processor or equivalent device must seek permission to access the location in which that copy exists, ensuring cache coherency. If the first cache content is required by a processor (e.g., when a cache hit occurs in the second cache for the first cache content), room is again made available, if required, in the first cache by selecting a second cache content from the first cache and moving it to the second cache.

Abstract: Live pointer information for a stream of bytecodes is precomputed for each bytecode. The precomputed full live pointer information is stored only for bytecodes at predetermined intervals in the stream. Between the bytecodes for which full live pointer information is stored, changes in the live pointer information produced by each bytecode are encoded using a suitable compressive coding and stored. Later, when a program which needs the live pointer information, such as garbage collection, is initiated, the full live pointer information for the nearest bytecode preceding the desired bytecode boundary is retrieved along with the intervening coded changes. The changes are decoded and applied to the retrieved live pointer information to generate the live pointer information at the desired bytecode boundary.

Abstract: This invention describes a link-by-link flow control method for packet-switched uniprocessor and multiprocessor computer systems that maximizes system resource utilization and throughput, and minimizes system latency. The computer system comprises one or more master interfaces, one or more slave interfaces, and an interconnect system controller which provides dedicated transaction request queues for each master interface and controls the forwarding of transactions to each slave interface. The master interface keeps track of the number of requests in the dedicated queue in the system controller, and the system controller keeps track of the number of requests in each slave interface queue. Both the master interface, and system controller know the maximum capacity of the queue immediately downstream from it, and does not issue more transaction requests than what the downstream queue can accommodate.

Abstract: To simulate a bus of a circuit, a number of virtual bus stubs ("VBSs") each post simulated bus signals as a single step and execution of the simulation system which includes such a VBS continues. As a subsequent, separate step, the VBS substantially immediately thereafter reaps a resolved simulated bus state. Synchronization in such a system is achieved by grouping into zones all VBSs which collectively represent the simulated state of a single bus. Each VBS has one of four states, namely, reap running, reap stopped, post running, post stopped. When a VBS posts, it is determined whether any other VBS of the same zone has yet to reap a previously resolved simulated bus state. If such a VBS exists, the posting VBS moves from reap running state to a post stopped state and execution of the simulation system containing the posting VBS is suspended until the last VBS of a zone reaps the previously resolved simulated bus state.

Abstract: A system for avoiding exceptional conditions during execution of a program comprises an execution environment for executing the program and a fix-up code generation subsystem. The program comprises an instruction stream comprising a series of instructions, and the execution environment includes an exceptional condition detector for detecting at least one predetermined type of exceptional condition in connection with execution of each instruction in the instruction stream. The fix-up code generation subsystem is responsive to detection by the execution environment of an exceptional condition of the predetermined type in connection with execution of an instruction in the instruction stream for generating fix-up code which, when processed, would avoid the exceptional condition of that predetermined type, and substitutes the fix-up code in the instruction stream for the instruction in the instruction stream for which the at least one exceptional condition was detected.

Abstract: A number of methods and apparatus for managing clients of a computer server. In particular, the usher implements an orderly and predictable server deactivation and/or shut down strategy in generally the following manner. The usher continuously maintains a transaction counter indicative of the number of clients actively utilizing services. For example, the usher may increment the transaction counter when a service is requested and then decrement the transaction counter when a service is completed or terminated. However, at some point in the server operation, the usher may receive a lock up request. This may occur because a client has invoked a deactivation and/or shut down operation, or the server may decide to shut down itself. In any event, upon receiving the lock up request, the usher will not perform any new client requests. Thus the usher controls the accessibility of the server to external clients by preventing new client requests for service in preparation for shut down.

Abstract: Proximity radar mounted in a vehicle determines the location of other vehicles. Other vehicles detect their own positions and broadcast those positions to all surrounding vehicles. Vehicle position data is plotted on a moving map so the driver can see the location of other vehicles, in some cases with an icon color which matches vehicle color(s). A driver can open a communication link with drivers who are projected to constitute a collision threat. A fixed radar unit can be positioned at blind intersections and broadcast vehicle location information for vehicles not equipped with the ability to track their own locations.

Abstract: Change control in a software release stream is managed by a computer implemented Request To Integrate (RTI) system, including at least one user unit having an input unit and a display. A server unit which is connected to the user unit(s) creates and stores RTI files representing requests to integrate changes into the software release stream, and enables a selected RTI file to be displayed on the display unit under control of the input unit. The server unit includes a database in which the RTI files are stored under the Source Code Control System (SCCS), and a search engine for searching the database and displaying selected RTI files and their histories. The RTI files are in World Wide Web (WWW) HyperText Markup Language (HTML) text format, and are accessible through a WWW browser in the user unit(s) and a cooperating WWW server in the server unit. The server unit stores and executes a program including a WWW home page, and developer, evaluator and gatekeeper pages which are accessible through the home page.

Abstract: Spell checking of network addresses such as Uniform Resource Locator (URL) addresses is provided at three levels. Each is invoked when a connection to the specified network address is unable to be established. At a client level, the specified URL is compared with URL's previously successfully used to find candidate misspellings. At a server level, directory and file names are checked against corresponding components of the URL to which connection was requested to return a list of candidate correct spellings to the requestor. Excluded from the list returned to the requestor are the correct spellings of "hidden" files to which general access is not desired. At a network access provider level, information about URL's successfully used by all customers is accumulated and used to provide a candidate list of correct spellings to a user. Older entries are periodically pruned from the database to control size.

Abstract: A system and method for preventing a computer system from overheating when a processor or software controlling the processor which controls the cooling system fails. The apparatus utilizes a watchdog timer which receives periodic signals confirming proper operation of the processor. When these status signals are not received, the watchdog timer transmits signals causing the cooling system that prevents overheating of the computer system.

Abstract: A method and apparatus for coupling object state and behavior in a DBMS is provided such that an object's class definition, behavior information, and state information are included in the DBMS. An object is instantiated using an object class definition, state information, and behavior information from the DBMS. In addition, an object can be stored in the DBMS by storing its class definition along with its state and behavior information in the DBMS. The behavior information stored in the DBMS can be used within and without the DBMS environment.

Abstract: A handheld computing device is used to copy files from the screen of a fixed computer. The display of the handheld device is linked to that of the underlying computer and file and directory icons together with their underlying files are copied to the handheld device. Files from the handheld device can also be transferred to the fixed computer. When a user is running a program on the fixed computer, he may capture the state of that computer and transfer everything needed to permit execution of that program to continue uninterrupted on the handheld device. Thus files and executing programs may be lifted from the fixed computer and used on the handheld device.

Abstract: A method for handling an overflow condition in a processor is disclosed. A first plurality of signal data is packed into a first memory location so as to form a first word. A second plurality of signal data is packed into a second memory location so as to form a second word. A bitwise operation is then performed between the first word and the second word to produce a result. The result of the operation is then stored in a k bit memory location so as to form a third word. The third word is then shifted left (k-9) bits. A bit mask is then obtained by arithmetic shifting the third word right (k-1) bits. A logical OR operation is then performed between the bit mask and the result.

Abstract: An electronic circuit verification system and method includes an HDL circuit simulator and a circuit simulation verifier that pass control back and forth between each other, and that cooperate so as to perform circuit verification tasks than would be very difficult to perform using only the HDL circuit simulator. The circuit simulation verifier is coupled to the HDL circuit simulator so as to control the HDL circuit simulator's operation, including specifying conditions under which the HDL circuit simulator is to stop simulation of a specified circuit and specifying input signal waveforms to be used by the HDL circuit simulator. The circuit simulation verifier receives signal waveforms generated by the HDL circuit simulator for specified watched signals. The circuit simulation verifier then determines whether predefined logical combinations of the watched signals meet specified operational correctness and/or performance criteria within specified time frames.

Abstract: A multiprocessor computer system has a multiplicity of sub-systems and a main memory coupled to a system controller. Some of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a respective set of master cache tags (Etags), including one Etag for each data block stored by the cache memory. Each data processor includes an interface for sending memory transaction requests to the system controller and for receiving cache transaction requests from the system controller corresponding to memory transaction requests by other ones of the data processors. The system controller includes transaction activation logic for activating each said memory transaction request when it meets predefined activation criteria, and for blocking each said memory transaction request until the predefined activation criteria are met.

Abstract: A workflow or product navigation system includes a single top-level screen which allows access to all aspects of the product information through selection of a single entry. The top-level screen includes a menu bar, a plurality of selectable icon push buttons in an icon area for directing inquiry to all aspects of the product information, and a product listing area. A user may select from several orderings of the icons to most efficiently access the product data. In particular, the icons are arranged in a preselected order as determined according to a business unit default definition. The user may select an alternative user-defined selection and ordering of icons, or a list of all icons in a predefined, fixed order. The icons on the top-level screen convey many details regarding the status of the product information. An icon, on its face, designates the user-access status of the information as read-write or read-only access. If a user has no access to information underlying the icon, no icon is displayed.

Abstract: A system and method for efficiently specifying vertex information for a three-dimensional graphical object which includes a plurality of geometric primitives. The method comprises organizing a first subset of the object's vertices into a strip of geometric primitives (typically triangles). The method next includes representing vertices of the strip by encoding a plurality of commands into a data stream. These commands are usable, during decompression, to reassemble the strip of primitives from a list of vertices. Selected commands specify that attributes of a particular vertex (position, color, normal value, etc.) are to be stored into a mesh buffer for use in forming subsequent primitives. The mesh buffer includes a fixed maximum number of memory locations which are accessible during the decompression process. In one embodiment, vertex parameters are "pushed" on to the mesh buffer, which is organized as a stack.