Abstract: In a processor speculatively executing instructions which specify logical addresses, a method and apparatus for speculatively converting logical addresses to physical addresses. The processor has a register window movable within a register file, a window pointer register maintaining a value corresponding to the location of the window in the register file, a speculative window pointer register maintaining a speculative value of the window pointer register. A controller identifies an instruction expected to modify the value in the window pointer register, and in response to identifying the instruction the controller modifies the speculative value. A mapper, coupled to the speculative window pointer register, converts the instruction specified logical addresses to physical addresses based on the speculative value contained in the speculative window pointer register.

Abstract: Apparatus methods, systems and computer program products are disclosed to provide electronic mail systems with the capability to act on previously-sent messages that have passed beyond the scope of control of the sending e-mail system.

Abstract: In hardware SRT division and square root mantissa units maximal quotient selection overlapping for three quotient digits per cycle are used. An effective radix-8 implementation cascades three partial remainder computation circuits and overlaps three quotient selection circuits. Two carry save adders speculatively compute the possible resulting partial remainders corresponding to each possible value, -1, 0, and +1, of the quotient digit by adding the divisor, not adding anything, and adding the two's complement of the divisor, respectively, thus shortening the critical path of a single SRT iteration producing a single quotient digit. The propagation delays of two carry save adders which speculatively compute the possible resulting partial remainders are masked by a longer delay through quotient selection logic.

Abstract: A method and system for resizing images in a computer system. A plurality of buffers are dynamically created in the memory of the computer system. Among the created buffers are a horizontal sampling buffer and two vertical sampling buffers. The horizontal sampling buffer is filled with data from a plurality of rows of the source image. The horizontal sampling buffer is composed of sub-buffers, each constituting a subset of the horizontal sampling buffer. Each sub-buffer is bytewise transposed to provide easy access to different channels of the image data. A filter is then applied to the transposed data with a result being stored in another buffer. The filtered data is then retransposed to assume its original configuration. The retransposed data is stored in a vertical sampling buffer previously created. The foregoing steps are repeated to fill a second vertical sampling buffer.

Abstract: A communications driver is provided for establishing communications sessions between a computer system and a remote device, such as another computer system. The computer system includes a plurality of ports which are connected to a number of diverse types of communications media. At least one of the ports comprises a network port controlled by a network socket driver, so that the communications driver can be used in connection with lower-level networking drivers which may be provided by a variety of manufacturers. The communications driver selectively establishes a communications session such that the computer system will operate as a terminal with the remote device over one of the communications media, as selected by an operator. The communications driver initially enables the operator to identify a communications medium and a remote device, and the driver thereafter selects one of the ports in response to identification by the operator of a communications medium and a remote device.

Abstract: Apparatus and methods are disclosed for performing time-reversed scheduling of a data dependency graph representing a target program instruction loop in an optimizing compiler. The instruction scheduling function is the modulo scheduling function of an optimizing compiler and it is noted that the time-reverse transforms preserve all modulo constraints. Most modern microprocessors have the ability to issue multiple instructions in one clock cycle and/or possess multiple pipelined functional units and typically contain multi-level memory devices such as on-chip cache, off-chip cache as well as main memory. For such microprocessors this invention can, where applicable, accelerate the process of modulo-scheduling loops in the target program code. The invention consists of a technique to transform the data dependency graph of the target program instruction loop in order to produce an improved schedule of the loop instructions.

Abstract: In a compression system, three-dimensional geometry is first represented as a generalized triangle mesh, a data structure that allows each instance of a vertex in a linear stream to specify an average of two triangles. Individual positions, colors, and normals are quantized, preferably quantizing normals using a novel translation to non-rectilinear representation. A variable length compression is applied to individual positions, colors, and normals. The quantized values are then delta-compression encoded between neighbors, followed by a modified Huffman compression for positions and colors. A table-based approach is used for normals. Decompression reverses this process. The decompressed stream of triangle data may then be passed to a traditional rendering pipeline, where it is processed in full floating point accuracy.

Abstract: A composite computer housing protects electronic components against shock and vibration. The housing has a midplane which divides the housing into a chassis section and a mainboard section. The chassis section holds hard disk drives. The mainboard section holds a mainboard, cards, a processor unit and other electronic components. A composite side cover assembly, having multiple layers, encloses the housing and provides a shell to inhibit flexion of the housing. The side cover presses against any number of the electronic components in the mainboard section to minimize vibration of these components and to enable the electronic components to provide internal support to the housing.

Abstract: An enterprise electronic calendar uses new enterprise protocols and mechanisms to implement the new enterprise protocols in an enterprise setting. The enterprise electronic calendar may perform activities such as automatically performing simple tasks that can be programmed. The enterprise electronic calendar works closely with new enterprise electronic calendar protocols in order to best support an enterprise and supports databases for a large organization where individuals must work towards common tasks. In a presently preferred embodiment of the present invention, a collection of four components closely interact with each other. The components are software based and reside in computers, workstations and palmtops linked through some type of network. The components include a timestamp controller (TSC), a graphical user interface (GUI), a protocol checking process (PCP) and a system administrator interface (SAI). Application as a manager of events in a distributed system is also provided.

Abstract: A merge computer instruction is capable of interleaving respective bytes of two four-byte words and is used once to group most significant bytes and least significant bytes of first and second pixel components represented in a two-byte format and to group most significant bytes and least significant bytes of third and fourth pixel components represented in the two-byte format and a second time to group the most significant bytes of the first, second, third, and fourth pixel components and to group the least significant bytes of the first, second, third, and fourth pixel components. The least significant bytes of the first, second, third, and fourth pixel components represent the first, second, third, and fourth pixel components in a one-byte format and are stored as the respective pixel components in the one-byte format. Thus, four pixel components are converted from a two-byte format to a one-byte format using only two computer instructions.

Abstract: Methods, and systems, and computer program products for displaying and editing picklists in a drop-down menu of a graphical user interface (GUI) of a computer. The drop-down menu allows a user to see a list of entries in a picklist section and to select an option to remove entries from the picklist section, to minimize clutter. The picklist section filters out redundant entries which are similar though not textually equivalent, to eliminate confusion in file lists and lists of recently used e-mail.

Abstract: A system and method for scrolling in a picture which is larger than MPEG standard in length or width or both in a video system, such as an interactive television system. In the preferred embodiment, the interactive television system comprises a video delivery system for providing video content, and at least one subscriber television including a display screen, wherein the subscriber television is coupled to the video delivery system. The video delivery system provides the compressed picture. The compressed picture has a length and/or a width which is larger than MPEG standard or alternatively is larger than the desirable viewing size. The compressed picture is subdivided into slices and possibly groups of slices such that the image may be smoothly scrolled. The subscriber television receives the compressed picture and operates to scroll in the compressed picture as desired by the user.

Abstract: Circuits and methods for a zero setup time storage element are disclosed. A storage element having a data input terminal, a clock input terminal and a data output terminal is able to capture a logic value of a data signal on the data input terminal with a substantially zero setup time at an active edge of a clock signal. Furthermore, some embodiments of the storage element are able to drive the captured logic value until the next active edge. One embodiment of the storage element includes a control circuit coupled to an output driver circuit. Depending on the state of the data input signal during an active edge, the control circuit can drives a first control signal to the output driver circuit or a second control signal to the output driver circuit. The output driver drives a data output signal on the data output terminal of the storage element based on the values of the control signals.

Abstract: Apparatus, methods, systems and computer program products are disclosed to simplify a computer user's handling of distribution lists for electronic mail messages. The invention provides the computer user with a mechanism for managing e-mail distribution lists. The mechanism includes facilities for suspending e-mail messages from a distribution list for a specified duration.

Abstract: An oscillator runaway detection circuit is provided with a synchronous delay line such that energy saving or sleep modes of operation are not mischaracterized as oscillator runaway. A Schmitt trigger monitors oscillator control voltage at a filter capacitor. If the control voltage is below a predetermined limit, indicating a possible runaway condition, a signal is output to a synchronous delay line. The output of the Schmitt trigger is propagated through the synchronous delay line comprising a plurality of flip-flops clocked by the system reference clock. The output of the synchronous delay line drives a transistor which in turn may charge the filter capacitor to reduce the control voltage and thus lower the frequency of the oscillator. A one-shot coupled to the clock tree monitors for clock activity in the clock tree.

Abstract: A system for resolving packet errors and busy acknowledgments for packets in a ring network, to maintain continued packet distribution on the network with support for strongly ordered, nonidempotent commands. Each consumer node on the network maintains a record of the sequence of packets that have passed through that node, and the state of each of the packets at the time it passed through, including a record of the last known good packet and its sequence number. When a producer node detects an error condition in an acknowledgment for a packet, resends all packets beginning with the last known good packet. Each consumer node is able to process or reject the resent packets, including packets that may already have been processed, which it is aware of due to the packet and state records for all packets.

Abstract: A control circuit to stop an integrated circuit internal clock includes a signal distribution trace connected to a clock stop pipeline. The signal distribution trace creates a large phase delay signal for a first integrated circuit internal clock cycle which activates the clock stop pipeline, and a small phase delay signal for a final integrated circuit internal clock cycle that deactivates the clock stop pipeline. The clock stop pipeline includes a first circuit component to generate an intermediate stop instruction in response to a clock stop command and the large phase delay signal of the first integrated circuit internal clock cycle. The intermediate stop instruction proceeds through the clock stop pipeline in response to clock cycles following the first clock cycle.

Abstract: The graphics applications of a 2-D graphics computer system provide each object to be rendered on a 2-D raster display with a pair of rendering reference coordinates (x and y), and a relative depth value (z). Additionally, the computer system is provided with a library of predetermined 2-D images and sounds, and a number of graphics toolkit routines. As the user "moves", the graphics toolkit routines render selected ones of the predetermined images based on x/z and y/z values of recomputed x and y rendering coordinates and the relative depth value z of the objects, and actuate the sounds if applicable based on their predetermined manners of rendering. As a result, the objects that are further away from the user will move slower than the objects that are closer to the user, thereby introducing the effect of parallax and added realism to the 2-D graphics computer system at a substantially lower cost.

Abstract: A method, in a computer network having a first plurality of nodes coupled to a common network infrastructure and a distributed shared memory distributed among the first plurality of nodes, for servicing a memory access request by a first node of the first plurality of nodes. The memory access request pertains to a memory block of a memory module that has a home node different from the first node in the computer network. The home node has a partial directory cache that has fewer directory cache entries than a total number of memory blocks in the memory module. The method includes the step of ascertaining whether the memory block is currently cached in the partial directory cache. If the memory block is currently cached in the partial directory cache, the first memory access request is serviced using a directory protocol. If the memory block is not currently cached in the partial directory cache, the first memory access request is serviced using a directory-less protocol.