Abstract: The present invention provides an "alert" interface for a component which can be safely "hot-plugged/unplugged" to an "alert" interconnect of an electrically powered system. The alert interface has a mating edge which includes daughter precharge/ground connectors, a daughter (engage) waning connector, a number of daughter signal connectors and a daughter engage connector. The alert interconnect includes corresponding mother connectors. The respective connectors of the interconnect and the interface are arranged so that they mate in the following exemplary order when the interface is hot-plugged/unplugged to the interconnect: precharge/ground connectors, warning connectors, signal connectors and finally engage connectors. When the daughter (engage) warning connector mates with the mother warning connector, the component sends an "engage warning" signal to the powered system.

Abstract: A multiprocessor computer system has data processors and a main memory coupled to a system controller. Each data processor has a cache memory. Each cache memory has a cache controller with two ports for receiving access requests. A first port receives access requests from the associated data processor and a second port receives access requests from the system controller. All cache memory access requests include an address value; access requests from the system controller also include a mode flag. A comparator in the cache controller processes the address value in each access request and generates a hit/miss signal indicating whether the data block corresponding to the address value is stored in the cache memory.

Abstract: In the present invention, a microprocessor controls a moveable output hopper with multiple paper slots attached to a laser printer. Print jobs of different users are directed to separate open slots by user name or other identifier corresponding to a particular user. A small LCD panel for each slot displays an identifier representing the user whose job is currently using the output slot. Incoming print data to the laser printer is monitored for a banner page. The user name or identifier is then extracted from the banner page, and if the current job is for a new user, the trays are moved and the print job is output to the first unused tray. A user name or identifier corresponding to the printed output is also displayed on an LCD panel corresponding to a particular tray. If all trays are full, print jobs are sent to a tray designated as the default/shared tray.

Abstract: An AC sequencer receives source AC voltage via a sequencer-mounted universally accepted connector, such as an IEC 309 compatible connector. Source AC is coupled by an AC connector plug and AC power cord from a wall socket to the AC sequencer via a mating connector. Although specifications for the AC power cord and AC connector will vary from country to country, the same AC sequencer may be used in many countries. Further, the AC sequencer receives control and status signals via sequencer-mounted universally accepted connectors, and can respond to signals that may be voltage-sourced, current-sourced, in addition to signals representing switch openings and closures. This permits a master server AC sequencer to be intelligently daisy-chained to remote slave units containing a similar AC sequencer, such that status information may be received from and control signals sent to the slave unit.

Abstract: A method and apparatus for providing address designations for a three dimensional computer system arranged in a plurality of planar layers is disclosed. Each layer comprises an incrementer for generating a layer identification value. A first layer has a starting value, representing the first layer identification value, and an incremental value which is added to the starting value to generate a second layer identification value. In this way, each incrementer on each layer is serially coupled to a next higher layer. A control processor accesses file information on each layer through use of the layer identification value. The register file identifies the layer as a memory module, processor module or input/output interface module. From the information contained within the register file, the control processor assigns an address to each of the layers. In addition, the control processor writes initialization parameters to the register file.

Abstract: The present invention provides a unified grammar for a speech interpreter capable of real-time speech understanding for user applications running on a general purpose microprocessor-based computer. The speech interpreter includes a unified grammar (UG) compiler, a speech recognizer and a natural language (NL) processor. The UG compiler receives a common UG lexicon and unified grammar description, and generates harmonized speech recognition (SR) and NL grammars for the speech recognizer and natural language processor, respectively. The lexicon includes a plurality of UG word entries having predefined characteristics, i.e., features, while the UG description includes a plurality of complex UG rules which define grammatically allowable word sequences. The UG compiler converts the complex UG rules (complex UG rules include augmentations for constraining the UG rules) into permissible SR word sequences and SR simple rules (simple rules do not include any augmentation) for the SR grammar.

Abstract: A distributed computer system in which a server application performs operations responsive to operation requests from a client application. The client application initially identifies an operation for the server application to perform with a short identifier of the operation. If the short identifier is ambiguous, the server application sends the client application a reply indicating that the short identifier was ambiguous. The client application responds by sending a long identifier which uniquely identifies the operation. Preferably, the short identifier of an operation is derived by performing a hash function on the long identifier of the operation. In object-oriented distributed systems, the operations are methods defined in objects supported by the server application.

Abstract: A software system manager to achieve second-order logical management of a software system model is described. The system relies upon a second-order logic system description that uses variable functors with specified import predicate arguments and export predicates. The second-order logical system description includes a second-order system model, a second-order rule set, and a second-order operation module. The second-order system model defines a set of existing program files, the second-order rule set defines a set of operations that can be performed on the existing program files, and the second-order operation module specifies an operation to be executed by the secondorder rule set on the set of existing program files. The second-order logic system description is used to generate a set of system construction commands. The system construction commands specify the commands necessary to transform the existing program files into intermediate object files that are used to produce an executable program.

Abstract: A diverse goods arbitration system and method allocates computer resources among bidding requesters. Bid slates are transmitted to an arbiter by users (requesters) requesting use of specified portions of the available computer resources. Each bid slate may contain a plurality of bids, each bid representing a requested set of resources and a bid price. The arbiter selects combinations of bids from the bid slates, where each bid combination consists of no more than one bid from each of the received bid slates. The arbiter rejects all bid combinations whose constituent bids exceed an established maximum allocation level for any computer resource. It then selects as a winning bid combination the bid combination having the highest total bid price. Computer resources are then allocated for a next time period based on the winning bid. Costs are allocating to each successful requester in accordance with a predefined opportunity cost function.

Abstract: A self-enabling latch includes a pair of pass transistors, a pair of cross-coupled inverters, an EXCLUSIVE-NOR logic gate and a differential amplifier. The pass transistors receive a differential input data signal which is selectively latched by the cross-coupled inverters. The EXCLUSIVE-NOR logic gate also receives the input data signal and compares it with the latched data signal to provide a control signal for the amplifier. The control signal is active when the present input data is different from the previously latched data. The amplifier, enabled by the active control signal, amplifies a differential clock signal to provide an enabling signal for the pass transistors which thereby present the new input data to the cross-coupled inverters for latching.

Abstract: Computers are manufactured with connectors in which are inserted at least one PCI expansion card to increase the capacity of the computer. A computer enclosure panel is formed with an opening for insertion and withdrawal of the card. The card has a cover which blocks the opening after the card has been plugged in. The invention provides a retainer clip mounted on the rear panel which, when in operative position, attaches to the panel and engages the cover to assist in holding the card in place. The clip has a bent spring which may be compressed to install and remove the clip. The invention further provides room for the tab conventionally extending outward of the card to extend outward of the enclosure so that the card may be located closer to the side panel, thereby conserving space within the enclosure. Computers as shipped from the factory many times are not provided with PCI cards and the opening in the panel is blocked by a removable blanking cover. The clip also holds the blanking cover in position.

Abstract: An embodiment of the present invention provides an efficient and robust way to incorporate new installation scripts into an existing operating system in order to install and reboot a system using a new platform specific kernel and new device specific drivers. The embodiment determines the platform architecture of the system and stores it in an address space of an existing operating system kernel. The embodiment also pre-processes a file with dynamic entries in order to generate device independent package names. If the platform architecture type stored in each package matches the platform architecture type stored in the kernel address space then the file system is used to install the files from the package onto the system. The existing operating system then reboots the system using the installed platform specific kernel.

Abstract: A three-layer BGA package includes a BGA Vss plane disposed between upper and lower BGA package traces, and also includes upper and lower BGA package Vss traces on the outer periphery of the BGA package. Vias electrically and thermally couple the BGA Vss plane to upper and lower BGA package Vss traces. Other vias electrically couple Vdd and IC signals from Vdd and signal traces on the upper and lower surfaces of the BGA package. Solder balls connected to the BGA package lower traces are soldered to matching traces on a system PCB. The periphery Vss traces, vias and solder balls help maintain current flow in the BGA Vss plane. In addition to providing a low impedance current return path (and thus reduced ground bounce and reduced IC signal delay time) for current sunk by an IC within the BGA package, the BGA Vss plane provides heat sinking. A four-layer BGA package further includes a BGA Vdd plane located intermediate the BGA Vss plane and the traces on the lower surface of the BGA package.

Abstract: A scalable packing circuit used to byte pack data transferred from a first storage element to a second storage element. The packing circuitry comprises a word packing circuit which receives data packets of a first bit width and stores them as data packets of a second bit width equivalent to the bit width of the second storage element. Concurrently, the word packing circuit eliminates invalid words included within the data packets from the first storage element. The packing circuit also includes a byte packing circuit which removes invalid bytes within the data packets of the second bit width before transferring the data to the second storage element for contiguous storage.

Abstract: A method and apparatus for browsing through a computer database on a computer system with a graphical user interface. The information to be browsed is displayed on a display screen. A browsing tool which resembles a magnifying glass is displayed on the display screen on top of the information. The browsing tool has a viewing lens with targeting crosshair and a "magnifying" reticle. When the browsing tool is moved about the screen, the information on the screen is shown in normal form. When the browsing tool comes to a rest, the information within the viewing lens of the browsing tool is modified depending on the current browsing tool mode. When the browsing tool is in magnification mode, the information within magnifying reticle is enhanced such that it fills the entire viewing lens of the browsing tool. When the browsing tool is in hierarchical browsing mode, the next lower level of the hierarchy is displayed within the viewing lens of the browsing tool.

Abstract: An integrated circuit package having an internal cooling device. The integrated circuit package includes a thermoelectric device that operates according to the Peltier cooling effect. The thermoelectric device includes a first plate and a second plate that are thermally connected by a plurality of conducting elements. A package substrate is attached to the first plate such that a chamber is formed. The second plate is disposed within the chamber apart from the package substrate. The second plate is cooled when power is supplied to the thermoelectric device. By disposing an integrated circuit chip on the second plate and evaluating the chamber, the integrated circuit chip may be cooled to a sub-ambient temperature without internal or external condensation.

Abstract: A technique is described for transmitting events over three or more conductors in which a sequence of activity of the conductors for information transfer is provided. To transfer information, the conductors are placed in an active state in a sequential manner, and then returned to an inactive state after each has been active in a time period short enough to prevent all conductors from being active at the same time.

Abstract: An apparatus and method calculate outcodes directly from an integral representation of a floating point number defining a certain coordinate of a point of an object to be displayed. Such calculations under software control are absent any Boolean conventional branch instructions which impede system performance and utilize an integer unit rather than a floating point unit so as to enable transformations of viewing parameters and calculations of outcodes to be performed in a concurrent manner.

Abstract: Three modes of moving and copying an object within an application or between applications are provided to a computer system having a graphical user interface. The three modes of moving/copying are: a) unmodified move and unmodified or modified copy from a data pane of a first display window to a "destination bin" of a second display window, b) unmodified copy from a "source bin" of a first display window to a data pane of a second display window, and 3) unmodified copy from a "source bin" of a first display window to a "destination bin" of a second display window. The three modes of moving/copying are performed with a CPU coupled to a display device, a cursor control device and a keyboard. Visual feedback is provided to the user throughout the different modes of moving and copying.