Abstract: A full width single in-line memory module (SIMM) for dynamic random access memory (DRAM) memory expansions is disclosed. A printed circuit board having a multiplicity of DRAM memory elements mounted thereto is arranged in a data path having a width of 144 bits. The SIMM of the present invention further includes on-board drivers to buffer and drive signals in close proximity to the memory elements. In addition, electrically conductive traces are routed on the circuit board in such a manner to reduce loading and trace capacitance to minimize signal skew to the distributed memory elements. The SIMM further includes a high pin density dual read-out connector structure receiving electrical traces from both sides of the circuit board for enhanced functionality. The SIMM is installed in complementary sockets one SIMM at a time to provide memory expansion in full width increments.

Abstract: An apparatus is disclosed for cooling a multi-chip module using embedded heat pipes. Semiconductor chips are disposed into the multi-chip module through cavities in the module substrate. The semiconductor chips engage heat pipes embedded within the substrate. The heat pipes conduct heat away from the semiconductor chips through a heat conductive bonding layer.

Abstract: In the image generation method and apparatus of the present invention, an image generation apparatus is provided in which a digital halftone cell of threshold values is generated and broken down into a plurality of tiles determined from the locations of the four corners of the halftone cell. The tiles when put together form a bounding box around the halftone cell. These tiles are arranged into a threshold array of threshold values wherein the width of the array is equal to the number of threshold values in a sequence of threshold values across a row of contiguous tiles and the height of the array is equal to the greatest common denominator of the x axis increment and y axis increment between vertices of the halftone cell.The threshold array is stored in memory for subsequent reference during the halftoning process.

Abstract: In the memory access unit of the present invention, the memory request logic is centralized in the memory management unit (MMU). The MMU instructs the MCU, which interfaces directly with the DRAMs, on the type of memory access to perform. By centralizing the memory requests, the MMU is able to maintain an account of each memory access, thereby providing the MMU the means to determine if a memory access fulfills the requirements of a fast page mode access before a request is made to the MCU. The MMU comprises the row address comparator which can execute the row address comparison in parallel with the cache lookup. Therefore, if the cache lookup determines a memory access is required, a specific fast page mode memory access request can be made, without the memory controller incurring the additional delay of checking the row address.

Abstract: A method and apparatus for dithering vectors in which the dither matrix is aligned to the vector and not to the display coordinate space. The dither matrix is aligned to the vector according to the major axis of the vector. In a preferred embodiment the dither matrix is rectangular in shape to correspond to the shape of the vector. The vector aligned dither matrix ensures that the individual pixels which make up the vector are dithered with elements more likely to simulate the original intermediate intensities.

Abstract: An improved memory model and implementation is disclosed. The memory model includes a Total Store Ordering (TSO) and Partial Store Ordering (PSO) memory model to provide a partial order for the memory operations which are issued by multiple processors. The TSO memory model includes a FIFO Store Buffer for Store, and Atomic Load-Store operations. The Load operations are not placed in the FIFO Store Buffer. The Load operation checks for a value stored in the same location in the FIFO Store Buffer; if no such value is found, then requested value is returned from memory. The PSO model also includes a Store Buffer for Store, and Atomic Load-Store operations. However, unlike the TSO model, the Store Buffer in the PSO model is not FIFO. The processors in the PSO model may issue the Store and Atomic Load-Store in a certain order; however, such operations may be executed by memory out of the order issued by the processors. The execution order is assured only by address matching and the STBAR operation.

Abstract: A bus architecture and protocol for integrated data and video memory. A high speed dedicated memory bus is coupled to a memory controller. The memory controller is in turn coupled to a multiple processor bus interconnecting one or more processors. Single in-line memory modules (SIMMs) incorporating dynamic random access memory (DRAM), video RAM (VRAM), and static nonvolatile RAM (SRAM) are coupled to the memory bus. Bus control signals forming a bus protocol, and address and data lines from the memory controller are shared by all memory modules operating on the memory bus. Certain control signals invoke specific operations on memory modules or are ignored, depending on the type of memory module receiving the control signal. The memory modules incorporate the consistent protocol by virtue of a consistent control signal pin out. The SIMMs further incorporate buffering and conversion functions, thereby relieving the memory controller of service overhead associated with these functions.

Abstract: A multiple bus architecture for flexible communication between processors, memory subsystems, and specialized subsystems over multiple high performance communication pathways. The multiple bus architecture enables flexible communication between processors and devices coupled to a multiprocessor bus, a system interconnect bus, an external bus, an input/output bus, and a memory subsystem. Processor modules coupled to multiprocessor bus slots access the memory subsystem over the multiprocessor bus. System interconnect modules coupled to system interconnect bus slots access the memory subsystem via the system interconnect bus, and the multiprocessor bus. Processor modules coupled to multiprocessor bus slots access devices on the external bus via the system interconnect bus.

Abstract: The present invention discloses an isolating device comprising an isolator designed to reciprocatively support the housing of a computer by means of an insert member inserted into the body of the isolator and having the bottom end of the insert member compressibly and extensibly supported therein. The insert member comprises a base mounted to the bottom of the computer housing and two stems extending downward from the base for insertion into two insert cavities within the body of the isolator. Square-like flanges are provided on the bottom corners of the stems such that they define a reception cavity between the flanges at the end of the stems and an upward rim on the opposing sides of each stem. The isolator comprises two insert cavities within the body of the isolator having a plug extending upward from the bottom wall of each cavity for insertion into the support cavities of the stems when the insert member is inserted into the isolator.

Abstract: When an arithmetic operation is to be performed, the operands are concurrently sent to the arithmetic unit to perform the complex arithmetic operation and into an operand check mechanism which determines whether one or both of the operands is a specific instance of a trivial operand. If one of the operands is a specific instance of a trivial operand, the complex arithmetic operations are halted and the check mechanism rapidly outputs the result of the arithmetic operation according to the trivial operand detected. Consequently, the need to perform complex arithmetic operations on trivial operands is avoided.

Abstract: An I/O cache is provided to a computer system comprising a main memory and a number of DVMA/DMA I/O devices for caching I/O data between the main memory and the DVMA/DMA I/O devices. The I/O cache selectively caches the I/O data in accordance to the device class types of the DVMA/DMA devices. The I/O cache comprises an I/O cache data array, an I/O cache address tag array, an I/O cache mapper, and I/O cache control logic. The I/O cache data array comprises a number I/O cache lines, each having a number of I/O cache blocks, for storing I/O data between the main memory and the DVMA/DMA devices. The I/O cache tag comprises a number of corresponding I/O cache address tag entries, each having a number of I/O cache address tags and associated control information, for storing address and control information for the I/O data stored in the I/O cache lines.

Abstract: An easy to engage and disengage dual height card retainer that facilitates removal of daughterboards is disclosed. Daughterboards have a two-tier staggered arrangement above the motherboard. Each daughterboard has a signal transfer end that electrically connects to the motherboard through one of the dual height bus connectors, and a back panel connector end that couples to the back panel with an accessory connector or with a filler panel that functions as an electromagnetic interference shield. Dual height card retainers that require no tools to operate function as retaining means to prevent daughterboards from working lose from bus connectors during shipment.

Abstract: A modular circuit board placement system is disclosed that provides for flexible placement of daughterboards, for minimal bus signal path lengths between motherboard and daughterboards, and for ease of installation and removal of daughterboards. The placement system employs dual height bus connectors, a stepped back panel, easy to engage and disengage dual height card retainers, filler panels that also function as module mounts, and multipurpose circuit card handles that facilitate removal of daughterboards. Daughterboards have a two-tier staggered arrangement above the motherboard. Each daughterboard has a signal transfer end that electrically connects to the motherboard through one of the dual height bus connectors, and a back panel connector end that couples to the back panel with an accessory connector or with a filler panel that functions as an electromagnetic interference shield.

Abstract: Individual multi-cycle statements or complex arithmetic units such as dividers, multipliers and adders are replaced with a fast, single-cycle cache lookup. This cache contains the results of a specific arithmetic operation using specified operands. These operands were previously utilized by the processor to perform an earlier, but duplicative, operation. Before performing a specific arithmetic operation, the cache is referenced to determine if the operation has been performed. If the operation has been performed, the result is output without the need to perform the multi-cycle arithmetic operation. Preferably, the operands of the arithmetic operation are hashed to form an index to perform a cache lookup. If the portion of the cache indicated by the index registers a "hit", the stored arithmetic result is output. When a cache miss occurs, the arithmetic operation is completed by the arithmetic unit. The result may then be stored in the cache indexed by the operands.

Abstract: An improved high speed, high density Dynamic Random Access Memory (DRAM) electrical signal interconnect structure which has particular application to computer systems which employ Single In-line Memory Modules (SIMMs). The structure contains an on-board buffer for driving time critical signals from a single source and further includes innovative signal trace routing having approximately equivalent minimum distance signal line lengths and vias to memory modules on the front and back surfaces of the circuit board resulting in a high speed, high density SIMM with clean rising/falling signal edges.

Abstract: A method and apparatus for determining a uniform step size with respect to pre-transformation derivative bounds for tessellation of a graphic primitive wherein the step size results in triangles which meet post-transformation thresholds. To maximize the efficiency of rendering curved surfaces while ensuring that the tessellation criteria is met, a maximum scale value for the non-linear transformation between device coordinate (DC) and lighting coordinate (LC) space is determined and utilized to translate the tessellation threshold in DC space to a tessellation threshold value in LC space. Information regarding the curved surface to be rendered is transformed to the LC space from the model coordinate (MC) space. The derivative bounds of the curved surface, and the tessellation threshold value are utilized to determine the uniform step size to tessellate triangles representative of the curved surface.

Abstract: In a computer system, an arrangement for storing condition signals indicative of the position of a pointing device and the condition of a button thereof, apparatus for comparing present condition signals generated by a pointing device with stored signals indicative of a previous condition of the pointing device, and apparatus responsive to the comparison of present condition signals generated by a pointing device for generating a pointer interrupt signal only if a change in the pointer condition has occurred.

Abstract: In a computer system where applications and data manipulated by the applications are implemented in an object oriented manner, an object type and its deriving attribute are stored as an entry in a table having an identifier. The object type table is in turn stored in a database. Similarly, the object type and its attribute values having corresponding attribute identifiers are stored as an entry in a table having an identifier. The object type attribute table is in turn also stored in a database. An object type deriving manager and an object type attribute values obtaining manager corresponding to the object type table and the object type attribute table are provided for deriving object type and obtaining object type attribute values respectively. A row getting interface routine and a column getting interface routine are provided for invoking the functions of the object type deriving manager and the functions of the object type attribute values obtaining manager.