Abstract: Disclosed herein are systems and methods for fast phase alignment and clock and data recovery. Systems and methods may include a fast phase alignment component configured to generate a selected phase signal based on a characteristic of an incoming signal. A clock and data recovery component may also be configured to receive the selected phase signal and perform a clock and data recovery function on the incoming signal using the selected phase signal.

Abstract: A method and system for controlling a pulverized coal fired boiler wherein the flow of a coal/air mixture flowing to each burner is monitored and transmitted to a distributed control system. The distributed control system also monitors and controls the position of dampers in a splitter that feeds the coal/air mixture to the burners. The dampers are controlled in a closed loop fashion to achieve a optimal boiler performance.

Abstract: This disclosure relates to the use of carboxylic acid hydrazide for de-bonding (e.g., detaching) polyurethane adhesives. The carboxylic acid hydrazide is present in the polyurethane adhesive as a solid in free form and is thus not incorporated in the polymer. When the adhesive is heated to a temperature of at least 80° C., the polymer is thermally degraded. With such an adhesive, components that are bonded in such a way can be detached in a simple method, by which the repair, the use or the recycling of the components is more easily possible.

Abstract: The present disclosure is directed to an exemplary interface description or structure of an inter-bay Substation Automation (SA) application. The interface of the application to other elements of the SA system, for example to a bay controller, IED, OPC server, HMI, and/or gateway, is examined to fully automate the inter-bay SA application configuration and implementation. A formal description or structure of the base SA system as for example, including an IEC 61850 SCD file can be used to generate a formal description of the interfaces of the inter-bay SA application to be engineered. Logical nodes can be connected to the process single line diagram and integrated into the SCD file of the base SA system, thereby generating an enhanced SCD file.

Abstract: An integrated circuit semiconductor device includes a substrate, a deep via within the substrate which is provided with a dielectric cladding in contact with the substrate, metal fill located within the deep via and defining an upper surface, interconnect wiring, and a dielectric layer located above the deep via and a void between the upper surface of the metal fill and the dielectric layer. The interconnect wiring layer contacts the metal fill laterally.

Abstract: A sensor system has a support that extends along an observation zone, a row of detection subassemblies arranged one after another on the support and having subcircuits for capturing detection events within respective observation subzones defined by the respective detection subassemblies, and a base circuit on the support. The detection subassemblies are controlled with an alternating voltage having a frequency that forms a carrier frequency based on which a signal dialog occurs between the subcircuits and the base circuit.

Abstract: An apparatus for detecting a reversion of direction of a relative movement between a periodic scale for defining a periodic field and a field sensor. The field sensor outputs first and second sensor signals. The first sensor signal is advanced from the second sensor signal if the periodic field moves in a first direction. The second sensor signal is advanced from the first sensor signal if the periodic field moves in a second direction. A determiner determines the difference between the first sensor signal and a signal corresponding to a temporal change of the second sensor signal or between the second sensor signal and a signal corresponding to a temporal change of the first sensor signal.

Abstract: A method for fabricating a field-effect transistor is provided. The method includes forming a substrate region, forming two terminal regions at the substrate region, one terminal region being a source region and the other terminal region being a drain region, forming two electrically insulating insulating layers, which are arranged at mutually opposite sides of the substrate region and are adjoined by control regions, forming an electrically conductive connecting region, which electrically conductively connects one of the terminal regions and the substrate region the conductive connecting region comprising a metal-semiconductor compound, leveling a surface by chemical mechanical polishing after forming the control regions, etching-back the control regions after polishing, and performing a self-aligning method for forming the metal-semiconductor compound in the etched-back regions, on the substrate region, and on a terminal region.

Abstract: Disclosed herein are techniques, systems, and methods relating to compensation of phase disturbances of a phase lock-loop during power ramp up or down of a power amplifier. More specifically, a phase lock-loop is described that is able to switch between type I and type II PLL modes depending on the power state of the power amplifier without introducing additional disturbances.

Abstract: A device for generating a session key which is known to a first communication partner and a second communication partner, for the first communication partner, from secret information which may be determined by the first and second communication partners, includes a first module operable to calculate the session key using a concatenation of at least a part of a random number and a part of the secret information. The device also includes a second module operable to use the session key for communication with the second communication partner.

Abstract: A decoder for decoding a concatenated code includes a storage input interleaver for storage-interleaving of received data using a storage interleaving operation. A data memory is coupled to an output of the storage input interleaver for temporary storage of storage-interleaved data. A first storage output interleaver is coupled to an output of the data memory for interleaving of data read from the data memory, and a plurality of processors are coupled to an output of the first storage output interleaver to access the data memory. Further, an encoder for generating a concatenated code sequence includes a code interleaver coupled to an input of the encoder for applying a code generation interleaving operation, a first convolutional encoder having an input coupled to an output of the code interleaver, and a storage interleaver coupled to an input of the encoder for applying a storage interleaving operation.

Abstract: The present disclosure relates to off-chip supply of calibration data.

Abstract: A communication device includes an application data interface, a first communication layer and a physical media interface. The first communication layer includes a first entity configured to process application data and a second entity configured to process operations, administrations and maintenance data. The communication device further includes a switching device. In a first power mode, the switching device couples the application data interface to the first entity of the first communication layer. In a second power mode, the switching device couples the application data interface to the second entity of the first communication layer.

Abstract: A circuit arrangement for signal mixing. One embodiment provides a circuit arrangement for mixing an input signal with at least one carrier signal. The circuit arrangement includes a current source and a current sink. The current source and the current sink have a mixer core coupled between them which provides cross-coupling between mixer input connections and mixer output connections.

Abstract: A device for epicardial support and/or the assuming of cardiac activity having a double membrane (1) consisting of an elastic inner membrane (2) and a non-expandable outer membrane (3) as well as a closed cavity (4) formed therebetween which can be inflated and deflated by means of a fluid exhibiting a first chamber (6) allocated to the right ventricle (5) and a second chamber (8) allocated to the left ventricle (7). With the objective of further developing a device of the type indicated so that it provides for simple device operability while maintaining the advantage of being able to augment only one ventricle, it is provided for the first chamber (6) and the second chamber (8) are connected to one another by at least one valve (9) in a dividing wall (10) separating the two chambers (6, 8).

Abstract: An apparatus and method for producing semiconductor modules is disclosed. One embodiment provides for bonding at least one semiconductor die onto a carrier including a support film strip, the support film having applied an adhesive layer to one of its surfaces to attach the semiconductor die, and a pressure tool to press the semiconductor die and the support film strip onto the carrier to permanently contact the at least one semiconductor die to the carrier.

Abstract: A semiconductor device exhibits a first metal layer, made of a first metal, with at least one contiguous subsection. At least one second metal layer, made of a second metal, is placed on the contiguous subsection of the first metal layer. The second metal is harder than the first metal. The second metal layer is structured to form at least two layer regions, which are disposed on the contiguous subsection of the first metal layer. The second metal exhibits a boron-containing or phosphorus-containing metal or a boron-containing or phosphorus-containing metal alloy.

Abstract: The invention relates to a process for the multi-stage production of diffusion-soldered joints for power components with semiconductor chips, the melting points of diffusion-soldering alloys and diffusion-soldered joints being staggered in such a manner that a first melting point of the first diffusion-soldering alloy is lower than a second melting point of the second diffusion-soldering alloy, and the second melting point being lower than a third melting point of a first diffusion-soldered joint of the first diffusion-soldering alloy.

Abstract: Semiconductor device test structures and methods are disclosed. In a preferred embodiment, a test structure includes a feed line, a stress line disposed proximate the feed line, and a conductive feature disposed between the stress line and the feed line. The test structure includes a temperature adjuster proximate at least the conductive feature, and at least one feedback device coupled to the temperature adjuster and at least the conductive feature.

Abstract: An encapsulated semiconductor package includes a substrate including a chip mounting area and inner contact pads on its upper surface and at least two semiconductor chips, each having an active surface with a plurality of chip contact pads and a passive surface. A first semiconductor chip is mounted on the chip mounting area. A spacer block including a first and a second mounting face lying in essentially parallel planes is positioned between and attached to the first semiconductor chip and a second semiconductor chip. The mounting faces of the spacer block have a rounded outline.