Patents Assigned to TECHNOLOGIES INC.
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Patent number: 11862495Abstract: The present invention relates to a monitor wafer measuring method and measuring apparatus. The monitor wafer measuring method comprises the following steps: fixing a product wafer, the product wafer having several alignment marks and product measuring sites corresponding respectively to the alignment marks; determining the product measuring sites according to the alignment marks; and placing a monitor wafer, a projection of the monitor wafer in a vertical direction being aligned with and coinciding with the product wafer. The present application can reduce or even eliminate positional errors of the monitor wafer during a measurement process, such that product-level measuring position accuracy can be achieved for the monitor wafer and further, the measuring machine itself and process changes can be monitored in a better way.Type: GrantFiled: June 16, 2021Date of Patent: January 2, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: He Zhu
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Patent number: 11864371Abstract: A method for manufacturing a semiconductor structure includes: providing a substrate, the substrate having a first surface and a second surface opposite to each other, and a transistor being arranged on the second surface; forming release holes in the substrate, the release holes extending into the transistors, bottoms of the release holes being located in channel regions of the transistors, and top surfaces of the release holes being flush with the first surface; and forming a conductive structure in the release holes.Type: GrantFiled: July 28, 2021Date of Patent: January 2, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Shuai Guo
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Patent number: 11859511Abstract: Airfoils and methods of cooling an airfoil are provided. The airfoil may comprise a spar; a coversheet on the spar; and a dual feed circuit between the spar and the coversheet. The dual feed circuit may include a first dam, a second dam spaced apart from the first dam along the chord axis of the spar, a first inlet disposed adjacent to the first dam, a second inlet disposed adjacent to the second dam, a circuit outlet disposed between the first inlet and the second inlet, and a plurality of diamond and/or hexagonal pedestals disposed on an outer surface of the spar. The diamond and/or hexagonal pedestals may form a plurality of cooling channels between the first inlet, the second inlet, and the circuit outlet. There may be no other circuit inlets are located between the first inlet and the second inlet.Type: GrantFiled: November 5, 2021Date of Patent: January 2, 2024Assignees: ROLLS-ROYCE NORTH AMERICAN TECHNOLOGIES INC., ROLLS-ROYCE CORPORATIONInventors: Brett Barker, Eric Koenig, Jerry Layne, Jeffrey F. Rhodes
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Patent number: 11863761Abstract: Adjusting communication channels used by camera to communicate with a base station are described. In one aspect, characteristics of communication channels can be determined and the operation of the camera can be adjusted to use a communication channel based on a comparison of the characteristics of multiple communication channels.Type: GrantFiled: January 25, 2022Date of Patent: January 2, 2024Assignee: ARLO TECHNOLOGIES, INC.Inventors: Joseph Amalan Arul Emmanuel, Peiman Amini
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Patent number: 11860415Abstract: Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects are provided. An example optical interconnect joins first and second optical conduits. A first direct oxide bond at room temperature joins outer claddings of the two optical conduits and a second direct bond joins the inner light-transmitting cores of the two conduits at an annealing temperature. The two low-temperature bonds allow photonics to coexist in an integrated circuit or microelectronics package without conventional high-temperatures detrimental to microelectronics. Direct-bonded square, rectangular, polygonal, and noncircular optical interfaces provide better matching with rectangular waveguides and better performance. Direct oxide-bonding processes can be applied to create running waveguides, photonic wires, and optical routing in an integrated circuit package or in chip-to-chip optical communications without need for conventional optical couplers.Type: GrantFiled: October 21, 2021Date of Patent: January 2, 2024Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.Inventors: Shaowu Huang, Javier A. Delacruz, Liang Wang, Guilian Gao
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Patent number: 11861543Abstract: Disclosed are various embodiments for optimizing cubic utilization when loading items into a loading space. A current loading configuration of the loading space can be determined according to image data obtained by 3D sensors. Item data (e.g., volume, mass, type, dimensions, etc.) can be determined for incoming items to be loaded into the loading space. The current loading configuration and the item data can be used to determine an item sequence and optimal placement location for the next item to be loaded such that a cubic efficiency of the loading space is maximized and amount of air gaps between items is minimized. The current loading configuration can further be used to determine if a sensing system or an item loading system needs to be repositioned. Whether the next item was placed in the optimal placement can also be verified based on subsequent image data obtained by the 3D sensors.Type: GrantFiled: December 4, 2020Date of Patent: January 2, 2024Assignee: AMAZON TECHNOLOGIES, INC.Inventors: Stavan Dholakia, Nicholas Hernandez, Minh Le, Jacob Lauer, Shivani Sheopory
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Patent number: 11864377Abstract: A semiconductor structure includes: a substrate, a first conductive layer disposed on the substrate, a second conductive layer disposed on a surface of the first conductive layer away from the substrate, and third conductive layers covering side walls of the first conductive layer and in contact with the second conductive layer. Contact resistance between the third conductive layers and the second conductive layer is less than contact resistance between the first conductive layer and the second conductive layer.Type: GrantFiled: September 17, 2021Date of Patent: January 2, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Chih-Cheng Liu
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Patent number: 11862276Abstract: The present application relates to the technical field of integrated circuits, and in particular, to a memory test method and a memory test apparatus. The memory test method includes: providing a to-be-tested memory, where the to-be-tested memory includes a plurality of memory cells; alternately writing a first write value and a second write value into a memory cell of the memory cells at a preset frequency; writing a test write value into the memory cell; judging whether a data read from the memory cell is the test write value, and determining that a capacitance-frequency characteristic of the memory cell is abnormal if the data is not the test write value. According to the present application, the capacitance-frequency characteristic of the to-be-tested memory is accurately tested, to improve the field of memory products.Type: GrantFiled: April 15, 2022Date of Patent: January 2, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Wei Huang, Chi-Shian Wu
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Patent number: 11864057Abstract: A network system receives a service request sent from a computing device of a user. The service request identifies a service to be provided by a provider and a service request location. In response to receiving the service request, the network system identifies a plurality of candidate locations. The network system selects the location from a plurality of candidate locations according to predetermined criteria including a frequency measurement of each candidate location. The network system replaces the service request location with the selected location. The network system sends the selected location to the computing device. Responsive to receiving an acceptance of the selected location from the computing device, the network system generates navigation instructions for the provider from a current location of the provider to the selected location.Type: GrantFiled: February 2, 2021Date of Patent: January 2, 2024Assignee: UBER TECHNOLOGIES, INC.Inventors: Neil Fernandes, Shivendra Pratap Singh, Krishna Aditya Gabbita, Aditya Somani
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Patent number: 11860073Abstract: Embodiments of the present disclosure relate to a wafer breaking method and a chip failure analysis method. The wafer breaking method includes: providing a wafer sample, which includes a first surface with a target point and a second surface opposite to the first surface; forming a first crack and a second crack, orthographic projection of which on the first surface are on the same straight line as the target point in a preset direction; forming a cutting slot, there is a preset distance between a bottom of the cutting slot and the first surface, and orthographic projection of the first crack and the second crack are on the same straight line as the cutting slot; and breaking the wafer sample along the cutting slot, such that the wafer sample is broken in the preset direction to obtain a cross section of the target point in the preset direction.Type: GrantFiled: April 25, 2022Date of Patent: January 2, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Wen-Lon Gu
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Patent number: 11862225Abstract: A comparison circuit includes a reference adjustment module, a signal receiving module, and a control module. The reference adjustment module is configured to receive a first reference signal and output a second reference signal. The reference adjustment module is further configured to receive an adjustment signal, and unidirectionally adjust the equivalent coefficient within a preset value interval when the adjustment signal is received. The signal receiving module is configured to receive the second reference signal and an external signal. The control module is configured to: receive an enable signal and the comparison signal; and during a period of continuously receiving the enable signal, when the comparison signal jumps, terminate the output of the adjustment signal.Type: GrantFiled: April 24, 2022Date of Patent: January 2, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Zhiqiang Zhang
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Patent number: 11860217Abstract: The present application relates to a test circuit, comprising: M stages of test units, first terminals of test units in each stage being all connected to a power wire, second terminals of test units in each stage being all connected to a ground wire, third terminals of test units in the first stage being connected to the power wire, and third terminals of test units in the ith stage being connected to fourth terminals of test units in the (i?1)th stage; wherein, the M and i are positive integers greater than or equal to 2.Type: GrantFiled: March 9, 2021Date of Patent: January 2, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: ChihCheng Liu
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Patent number: 11858823Abstract: The present invention is a process, a method, and system for recovery and concentration of dissolved ammonium bicarbonate from a wastewater containing ammonia (NH3) using gas separation, condensation, and crystallization, each at controlled operating temperatures.Type: GrantFiled: January 31, 2022Date of Patent: January 2, 2024Assignee: BION ENVIRONMENTAL TECHNOLOGIES, INC.Inventors: Dominic Bassani, Morton Orentlicher, Mark M. Simon, Stephen Pagano
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Patent number: 11862268Abstract: Embodiments of the present disclosure provide a test method and apparatus for a control chip, an electronic device, relating to the field of semiconductor device test technology. The method includes: reading first test vectors stored in a first target memory chip; sending the first test vectors to the control chip; receiving first output information returned by the control chip in response to the first test vectors; and acquiring a first test result of the control chip based on the first output information and the first test vectors corresponding to the first output information. By means of the technical solutions provided in the embodiments of the present disclosure, a memory chip can be used for storing test vectors for a control chip, so that a storage space for test vectors can be enlarged, and the test efficiency can be increased.Type: GrantFiled: October 15, 2020Date of Patent: January 2, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Chuanqi Shi, Heng-Chia Chang, Li Ding, Jie Liu, Jun He, Zhan Ying
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Patent number: 11862513Abstract: A manufacturing method of a semiconductor structure includes the following steps. A substrate is provided. A barrier layer is formed on the substrate. A sacrificial layer is formed on the barrier layer. An opening pattern is formed over the sacrificial layer by utilizing a photolithography process. The sacrificial layer is etched according to the opening pattern to form first trenches by using the barrier layer as an etch stop layer. A medium layer material is filled in the first trenches. The sacrificial layer is etched to form second trenches by using the barrier layer as the etch stop layer. A hard mask layer material is filled in the second trenches. The medium layer material is etched to form a hard mask layer by using the barrier layer as the etch stop layer.Type: GrantFiled: September 30, 2021Date of Patent: January 2, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Xifei Bao
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Patent number: 11862965Abstract: The present disclosure provides an electrostatic discharge protection circuit, a chip including a first pad and a second pad. The electrostatic discharge protection circuit includes a trigger unit and a discharge transistor. The trigger unit is connected between the first pad and the second pad, provided with a trigger terminal, and configured to generate a trigger signal when there is an electrostatic pulse on the first pad. The first pad is connected to a first voltage, the second pad is connected to a second voltage, and the first voltage is greater than the second voltage. The discharge transistor has a first terminal connected to the first pad, and a second terminal connected to the second pad, and discharges an electrostatic charge to the second pad when triggered by the trigger signal.Type: GrantFiled: May 25, 2022Date of Patent: January 2, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Qi'an Xu
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Patent number: 11862283Abstract: A sense amplifier includes a first switch unit, a second switch unit, and an amplifier-latch module. A first port of the amplifier-latch module is electrically connected, via the first switch unit, to a bit line connected with a storage unit, and a second port of the amplifier-latch module is electrically connected to a reference voltage signal via the second switch unit. The amplifier-latch module is configured to amplify a signal in a sensing amplification phase. The first switch unit is configured to transmit a voltage on the bit line to the first port before the sensing amplification phase. The second switch unit is configured to transmit the reference voltage signal to the second port before the sensing amplification phase, and disconnect an electrical connection between the reference voltage signal and the second port in the sensing amplification phase.Type: GrantFiled: August 22, 2021Date of Patent: January 2, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Ying Wang, Sunsoo Chi
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Patent number: 11863179Abstract: A voltage conversion circuit is provided. The circuit includes a first input module and a second input module. The first input module is connected to a first voltage and has a first input terminal for receiving an input signal and outputting a conversion signal, a high level of the input signal is a second voltage which is less than the first voltage; The second input module is connected to the first input module and has a second input terminal and an output terminal, the second input terminal is configured to receive a sampling signal, and the second input module is configured to sample the conversion signal according to the sampling signal and output an output signal via the output terminal.Type: GrantFiled: March 8, 2022Date of Patent: January 2, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Kangling Ji
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Patent number: 11862697Abstract: A method for manufacturing a buried gate and a method for manufacturing a semiconductor device are disclosed. The method for manufacturing the buried gate includes that: a trench is provided on an active region of a substrate; a gate structure is filled in a bottom of the trench, and a trench sidewall above the gate structure is exposed; an epitaxial layer is grown on the exposed trench sidewall with an epitaxial growth process, in which the epitaxial layer does not close the trench; and an isolation layer is filled in the trench.Type: GrantFiled: July 9, 2021Date of Patent: January 2, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Er-Xuan Ping, Jie Bai, Mengmeng Yang
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Patent number: D1009537Type: GrantFiled: February 3, 2023Date of Patent: January 2, 2024Assignee: HNI TECHNOLOGIES INC.Inventor: David Mehaffey