Patents Assigned to TECHNOLOGIES INC.
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Patent number: 11862516Abstract: A semiconductor structure manufacturing method according to the embodiments of the present application includes the following steps of: providing a semiconductor substrate; forming a first reaction layer on the semiconductor substrate; forming a second reaction layer on the first reaction layer; and thermally reacting at least a portion of the first reaction layer with at least a portion of the second reaction layer, to form an amorphous diffusion barrier layer. This amorphous diffusion barrier layer is an amorphous body with no grain boundary therein. As a result, the diffusion path for metal atoms is cut off, thereby improving the barrier effect of the barrier layer efficiently and solving the circuit performance issue caused by metal atom diffusion.Type: GrantFiled: September 21, 2021Date of Patent: January 2, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Huiwen Tang
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Patent number: 11862285Abstract: A sense amplifier, a memory and a method for controlling the sense amplifier are provided. The sense amplifier includes: an amplification module configured to read data in a storage unit on a first or second bit line; a control module electrically connected to the amplification module. When data in the storage unit on the first bit line is read, in a first amplification phase of the sense amplifier, the control module configures the amplification module to include a first current mirror structure and connects a mirror terminal of the first current mirror structure to the second bit line; when data in the storage unit on the second bit line is read, in the first amplification phase of the sense amplifier, the control module configures the amplification module to include a second current mirror structure and connects a mirror terminal of the second current mirror structure to the first bit line.Type: GrantFiled: September 14, 2021Date of Patent: January 2, 2024Assignees: ANHUI UNIVERSITY, CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Zhiting Lin, Jianqing Li, Jun He, Zhan Ying, Xin Li, Kanyu Cao, Wenjuan Lu, Chunyu Peng, Xiulong Wu, Junning Chen
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Patent number: 11862266Abstract: The present disclosure provides a chip detection method and a chip detection apparatus. The chip detection method includes: providing a chip to be tested, the chip including a power pump region, and the power pump region including a plurality of power pump structures; detecting a dim light signal emitted from the power pump region when the chip is in a preset working mode; and determining whether the dim light signal matches a corresponding power pump working mode in the preset working mode, and if not, confirming that the power pump region has a defect, the power pump working mode including a working state of the power pump structures in the power pump region.Type: GrantFiled: July 29, 2021Date of Patent: January 2, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Jianbo Zhou
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Patent number: 11858143Abstract: An autonomous mobile device (AMD) follows a user who may move among other people, change orientation, or move in and out view of a camera on the AMD. A predicted location of the user may be determined based on a previous location and previous movement. A proximity value is determined by the distance between a location in physical space of a user and the predicted location. An image from a camera is processed to determine a user depicted in the image and generate a feature vector (FV) of that depiction. A gallery of FVs of the user as viewed from different angles, poses, and so forth is stored. A similarity value is determined between a FV of an unidentified user in an image and the FVs in the gallery. The user may be identified using the proximity value and the similarity value.Type: GrantFiled: March 2, 2020Date of Patent: January 2, 2024Assignee: AMAZON TECHNOLOGIES, INC.Inventors: Chi Liu, Wei Wang, Rajesh Shankarrao Padgilwar, Ning Zhou, Kah Kuen Fu
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Patent number: 11862232Abstract: A circuit and method for data transmission, and a storage apparatus are provided. A mode register decoding module is configured to generate a mode register unselected enable signal, a mode register read enable signal, or a mode register write enable signal according to received mode register address information, a mode register read control signal, or a mode register write control signal. A mode register read-write module is configured to: cache data on data line according to mode register write enable signal in write state, and output selected data and unselected data after setting the unselected data to zero according to the mode register read enable signal and the mode register unselected enable signal in a read state. The logic gate module is configured to calculate an OR value of the data outputted by each mode register read-write module in the read state and output a calculation result.Type: GrantFiled: May 12, 2022Date of Patent: January 2, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Zhiqiang Zhang
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Patent number: 11857748Abstract: Methods and devices that provide enhanced delivery of a composition to a body region of a patient utilizing radiofrequency energy include directing a first electrode and a second electrode coupled to a radiofrequency energy source to a location proximate to the body region. Radiofrequency energy is provided in modulated pulses from the radiofrequency energy source to the body region from at least one of the first electrode and the second electrode to provide a delivery condition configured to enhance delivery of the composition. The composition is delivered proximate to the body region using a composition delivery element. Devices for enhance composition delivery are also disclosed.Type: GrantFiled: October 20, 2017Date of Patent: January 2, 2024Assignee: ASAHI MEDICAL TECHNOLOGIES, INC.Inventors: Wayne Ogata, Xiang Ian Gu, Steven Meyer
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Patent number: 11862279Abstract: A method for determining a repaired line and a repairing line in a memory includes the following: writing first preset data sets into respective lines in a normal region, and writing second preset data sets into respective lines in a redundancy region; repairing the lines in the normal region by using the lines in the redundancy region; reading data from the lines in the normal region after repairing; and determining a repaired line in the normal region and a repairing line in the redundancy region according to the data of the lines in the normal region, the data of the lines in the normal region after repairing, or the data of the lines in the redundancy region.Type: GrantFiled: February 17, 2022Date of Patent: January 2, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Bo Yang, Xiaodong Luo
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Patent number: 11862494Abstract: A crane monitoring system includes a first detection apparatus, a processing apparatus and a second detection apparatus. The first detection apparatus is configured to detect a position of a crane, to send a first detection signal when the crane is located above a Front Opening Unified Pod (FOUP) load port of a semiconductor processing device, and to send a second detection signal when the crane leaves a space above the FOUP load port. The processing apparatus is configured to generate a start control signal responsive to receiving the first detection signal, and to generate a stop control signal responsive to receiving the second detection signal. The second detection apparatus is configured to start a detection of whether there is a foreign matter between the crane and the FOUP load port after receiving the start control signal, and to stop the detection after receiving the stop control signal.Type: GrantFiled: September 8, 2021Date of Patent: January 2, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Wei Feng
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Patent number: 11861232Abstract: Embodiments of the present disclosure relate to the technical field of semiconductors and provide a storage system and a data writing method thereof. The storage system is configured to: enter a write data copy mode in response to a write-copy enable signal; if at least two groups of data in multiple groups of data exported from multiple data ports are a same in the write data copy mode, define the at least two groups of data as a category; generate an identification signal that is used to indicate a data copy; transmit one group of data in the category to an interface of a memory array; and disconnect a transmission path between a data port corresponding to another group of data in the category and another interface of the memory array, wherein the memory array, in response to the write-copy enable signal and the identification signal.Type: GrantFiled: April 4, 2022Date of Patent: January 2, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Kangling Ji
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Patent number: 11859153Abstract: A method for cleaning a substrate includes the following: exposing the substrate to a cleaning agent to remove impurities on a surface of the substrate; exposing the substrate to a dewetting chemical agent in a liquid phase to remove the cleaning agent on the surface of the substrate; solidifying the dewetting chemical agent in the liquid phase remaining on the surface of the substrate to obtain the dewetting chemical agent in a solid phase; and sublimating and removing the dewetting chemical agent in the solid phase.Type: GrantFiled: August 30, 2022Date of Patent: January 2, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Shih-Hung Lee
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Patent number: 11861451Abstract: A method for chip collection and a method for chip positioning are provided. The method for chip collection includes that: an image to be detected is obtained; chip position information of a comparison image with a highest matching degree with the image to be detected is obtained from a database; a position of each of detection regions in the image to be detected is obtained based on the chip position information; an image of the detection region is obtained based on the position of each detection region; it is determined whether the image of the detection region includes the chip code image; and when the image of the detection region includes the chip code image, a chip code corresponding to the chip code image identified and the chip code is stored in the database.Type: GrantFiled: September 6, 2022Date of Patent: January 2, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Yui-Lang Chen
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Patent number: 11862222Abstract: A refresh circuit includes: a refresh control module configured to receive a refresh command to output a row address refresh signal, the row address refresh signal being outputted a number of times of a preset value each time the refresh command is received; and further configured to receive a temperature signal to adjust the preset value, the higher a temperature represented by the temperature signal, the greater the adjusted preset value; a row addresser configured to receive the row address refresh signal and output a to-be-refreshed single-row address; and an array refresh device configured to perform a single-row refresh operation according to the single-row address and output a single-row refresh end signal after the end of single-row refresh.Type: GrantFiled: November 27, 2021Date of Patent: January 2, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Yinchuan Gu, Geyan Liu
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Patent number: 11862272Abstract: A local region to be repaired including the fail bit is determined. A preliminary repair LR circuit for repairing the local region to be repaired is determined (S210). A region level of the local region to be repaired is determined (S230) according to the number of available GR circuits other than any replacement GR circuit configured for replacing the preliminary repair LR circuit and the number of available LR circuits. It is controlled, according to the region level of the local region to be repaired, to repair the fail bit by the GR circuit or the LR circuit (S240).Type: GrantFiled: August 16, 2021Date of Patent: January 2, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Yui-Lang Chen
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Patent number: 11862284Abstract: The present disclosure provides a sense amplifier, a memory, and a data readout method, and relates to the field of semiconductor memory technologies. The sense amplifier includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first switch, a second switch, a third switch, and a fourth switch. During the offset compensation stage of the sense amplifier, the switching states of the first switch to the fourth switch are controlled so that the first NMOS transistor and the second NMOS transistor are configured to be in a cross-coupled amplification mode, and the first PMOS transistor and the second PMOS transistor are configured to be in a diode connection mode. The present disclosure enables to realize the offset compensation of the sense amplifier and improves the correctness of data readout by the memory.Type: GrantFiled: July 30, 2021Date of Patent: January 2, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Kanyu Cao, Sungsoo Chi, WeiBing Shang, Ying Wang
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Patent number: 11862228Abstract: A power supply circuit and a memory are provided. The power supply circuit includes a voltage source, multiple power supply circuits and a control circuit. The multiple power supply circuits are connected to the voltage source. If the voltage source is effective and the multiple power supply circuits are in an enable state, a voltage of a power supply terminal is pulled up to a preset voltage, and power is supplied to the load units during the pulling up process. A first-type power circuit enters the enable state if a first enable signal is received, and each of second-type power supply circuits enters the enable state if second enable signal is received.Type: GrantFiled: February 10, 2022Date of Patent: January 2, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES INC.Inventor: Rumin Ji
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Patent number: 11864373Abstract: A method for manufacturing a semiconductor structure and a semiconductor structure are provided. The method includes the following operations. A substrate is provided, includes a core region and a peripheral region. A preset barrier layer is formed on the substrate, and covers the core region and the peripheral region. At least a part of the preset barrier layer corresponding to the peripheral region is removed to expose a part of the substrate, and to take a reserved part of the preset barrier layer as a first barrier layer. A dielectric layer and a first conductive layer are successively formed on the first barrier layer and the substrate. A part of the dielectric layer and the first conductive layer on the first barrier layer are removed, to reserve a part of the dielectric layer and the first conductive layer on the first barrier layer closer to the peripheral region.Type: GrantFiled: January 20, 2022Date of Patent: January 2, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Mengmeng Yang, Jie Bai
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Patent number: 11862286Abstract: A data transmission circuit includes: a comparison circuit, configured to compare received first data on a data bus with received second data on a global data line and output a comparison result of whether a number of different bits between the first data and the second data exceeds a preset threshold; a data conversion circuit, configured to: if the comparison result indicates that the number of different bits exceeds the preset threshold, invert the first data and transmit the inverted first data to the global data line, and otherwise, transmit the first data to the global data line; and a read-write conversion circuit, configured to: if the comparison result indicates that the number of different bits exceeds the preset threshold, transmit data on the global data line to a complementary local data line, and otherwise, transmit data on the global data line to a local data line.Type: GrantFiled: January 27, 2022Date of Patent: January 2, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Liang Zhang
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Patent number: 11860220Abstract: A method for evaluating a Hot Carrier Injection (HCI) effect of a device is provided. The method includes, a ratio of a substrate current to a drain current of a first device at different gate-source voltages is acquired, and recorded as a first current ratio; a ratio of a substrate current to a drain current of a second device at different gate-source voltages is acquired, and recorded as a second current ratio, the second device is subjected to process parameter adjustment or device parameter adjustment relative to the first device; and an influence of the process parameter adjustment or the device parameter adjustment on an HCI effect of the device is determined based on the second current ratio and the first current ratio.Type: GrantFiled: July 9, 2021Date of Patent: January 2, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INCInventor: QiAn Xu
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Patent number: 11862237Abstract: A memory includes a bank, the bank includes a plurality of sections, each of the plurality of section includes a plurality of word lines, a plurality of bit lines, and a plurality of storage units arranged in an array, and each of the plurality of storage units is connected to one of the plurality of word lines and one of the plurality of bit lines; the bank is configured to: in a preset mode, in response to a control signal, activate each of a plurality of word lines in at least one target section of the bank, pull up or pull down a level of each of a plurality of bit lines in the target section, and pull a complementary bit line of each of the plurality of bit lines in the target section to a level opposite to a level of the plurality of bit lines.Type: GrantFiled: April 20, 2022Date of Patent: January 2, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Tianchen Lu
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Patent number: 11862229Abstract: A reading and writing method for a memory device and a memory device are provided. The memory device includes a memory chip. The reading and writing method of the memory device includes that: during operation of the memory chip, the temperature of the memory chip is measured, and a writing recovery time of the memory chip is adjusted according to the temperature.Type: GrantFiled: September 9, 2021Date of Patent: January 2, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Shu-Liang Ning