Abstract: A testing circuit includes: a first sampling module configured to receive a to-be-tested pulse signal, and generate a first sampled signal according to the pulse signal; and a second sampling module configured to receive the pulse signal, and generate a second sampled signal according to the pulse signal. The second sampled signal and the first sampled signal have a phase difference, the phase difference being equal to a pulse width of the pulse signal.

Abstract: A transmission circuit includes: an upper-layer clock bonding pad configured to transmit a clock signal; M upper-layer data bonding pads configured to transmit data signals; a lower-layer clock bonding pad electrically connected with the upper-layer clock bonding pad, and an area of the lower-layer clock bonding pad is smaller than that of the upper-layer clock bonding pad; and M lower-layer data bonding pads electrically connected with the M upper-layer data bonding pads in a one-to-one correspondence, and an area of a lower-layer data bonding pad is smaller than that of an upper-layer data bonding pad. The upper-layer clock bonding pad and the upper-layer data bonding pads are located on a first layer, the lower-layer clock bonding pad and the lower-layer data bonding pads are located on a second layer.

Abstract: A surface treatment method for quartz component includes: sandblasting the quartz component; ultrasonically treating the sandblasted quartz component to remove a sharp corner formed on the surface of the quartz component; immersion cleaning the quartz component; and drying the cleaned quartz component.

Abstract: A semiconductor structure includes a conductive structure. A method for preparing the conductive structure includes: forming a semiconductor conductive layer; forming a nitrile or isonitrile transition layer on the semiconductor conductive layer; and forming a metal conductive layer on the nitrile or isonitrile transition layer.

Abstract: A method for adjusting the memory includes: acquiring a mapping relationship between a temperature of a transistor, a gate voltage of the transistor, and an actual time at which data is written into the memory; acquiring a current temperature of the transistor; and adjusting the gate voltage, based on the current temperature and the mapping relationship, so that the actual time at which the data is written into the memory corresponding to the adjusted gate voltage is within a preset writing time.

Abstract: A method for regulating the memory includes operations as follows. A mapping relationship among temperatures of a transistor, body bias voltages of the transistor, and data writing time of the memory is acquired, a current temperature of the transistor is acquired, the body bias voltage is regulated based on the current temperature and the mapping relationship, to enable the data writing time corresponding to the regulated body bias voltage to be within a preset writing time.

Abstract: Embodiments of the present disclosure provide a memory and its manufacturing method. The memory includes: a substrate with a plurality of mutually discrete bitlines, the bitline including a bitline conductive layer and a bitline insulating layer which are stacked in sequence; and an insulating layer and capacitor contact holes, the insulating layer being located on sidewalls of the bitline conductive layers and sidewalls of the bitline insulating layers, the capacitor contact holes being located between adjacent ones of the bitline conductive layers, sidewalls of the capacitor contact holes exposing the insulating layer, an opening size of the capacitor contact hole gradually increasing in a direction along the substrate and towards the insulating layer.

Abstract: A memory includes: a control chip; and a plurality of storage chips, in which the plurality of storage chips are electrically connected with the control chip via a common communication channel, the plurality of storage chips include a first storage chip set and a second storage chip set, the storage chips in the first storage chip set are configured to perform information interaction with the control chip by adopting a first clock signal, the storage chips in the second storage chip set are configured to perform information interaction with the control chip by adopting a second clock signal, and phase of the first clock signal is different from phase of the second clock signal.

Abstract: A system and method for recognizing objects in an image is described. The system can receive an image from a sensor and detect one or more objects in the image. The system can further detect one or more components of each detected object. Subsequently, the system can create a segmentation map based on the components detected for each detected object and determine whether the segmentation map matches a plurality of 3-D models (or projections thereof). Additionally, the system can display a notification through a user interface indicating whether the segmentation map matches at least one of the plurality of 3-D models.

Abstract: A respiratory treatment apparatus generates an indication of inspiration or expiration based on a measure of motor current of a flow generator. In an example, first and second current signals are derived from the measurement. The first derived current signal may be a long term measure or average of current and the second derived current signal may be a short term measure or average of current. A processor 120 determines an indication of inspiration or expiration as a function of the first and second derived current signals. The function of the first derived current signal and the second derived current signal may be a comparison of the derived current signals. The derived signals may be determined by filtering. The indication of inspiration or expiration may serve as a trigger or cycle control for changing treatment pressure in synchrony with patient respiration without measured signals from pressure, flow or speed sensors.

Abstract: Disclosed is a voltage regulator, which makes a low dropout regulator stop working by controlling a sampling circuit of the low dropout regulator to break in a sleep mode, and makes an output voltage of the low dropout regulator follow an output voltage of a first bias voltage generating circuit by using a first MOS transistor connected between an voltage input end and an voltage output end of the low dropout regulator in a source follower structure, and is capable of controlling an output voltage of the whole voltage regulator by a generated bias voltage applied to the first bias voltage generating circuit by a first bias current source.

Abstract: A semiconductor structure includes a substrate, word lines, bit line contact plugs, and first isolation layers. The word lines are located in the substrate. A bit line contact hole is provided between two adjacent word lines. The bit line contact plugs are located in the bit line contact holes. The first isolation layers are located on side walls of the bit line contact holes and cover side walls of the bit line contact plugs.

Abstract: The present invention relates to an optoelectronic sensor used with light curtains for monitoring a sensing field. The optoelectronic sensor includes at least one optical unit having at least one radiation emitting element and at least one radiation receiving element and a control unit for processing an output signal generated by said radiation receiving element and for generating a defined sensor signal based on the output signal. The optical unit has a diagnostic unit including a monitoring unit operable to monitor at least one parameter indicative of an operational status of the optical unit. The diagnostic unit includes a processing unit operable to generate a communication signal indicative of said operational status, and the diagnostic unit is arranged in a separately housed, detachable plug-in module. The processing unit comprises a wireless communication interface for wirelessly receiving and transmitting communication signals.

Abstract: A convolutional neural network hardware acceleration device, a convolutional calculation method, and a storage medium are provided. The device includes an instruction processing element (1), a hardware acceleration component (2), and an external data memory element (3). The instruction processing element (1) decodes instructions, and controls the hardware acceleration component (2) to perform operations corresponding to decoded instructions. The hardware acceleration component (2) includes: an input buffer element (21), a data calculation element (22) and an output buffer element (23). The external data memory element (3) stores the calculation result output by the output buffer element (23) and transmits the data to the input buffer element (21).

Abstract: A cable retrieving system is disclosed for a charging station adapted for recharging an electric vehicle, the charging station comprising an electric cable and a plug for enabling an electrical connection with the electric vehicle, the system comprising a mechanical wire having a first end secured to the electric cable and a second end; an enclosure comprising an opening suitable for the mechanical wire and a pulling mechanism located in the enclosure, the pulling mechanism comprising a weight member located in the enclosure and mounted on a portion of the mechanical wire to thereby create a pulling force on the mechanical wire to thereby pull the electric cable towards the charging station.

Abstract: A triangulation scanner having an enclosure, a projector coupled to the enclosure and configured to emit a first light, and three cameras also coupled to the enclosure. The scanner further includes at least one processor to determine the three-dimensional coordinates in a local frame of reference based at least in part on receiving the first light.

Abstract: A fully depleted silicon on insulator (FDSOI) is employed to reduce diffusion leakage (e.g., gate induced drain leakage, junction leakage, etc.) associated with the diffusion regions of a pixel cell. The buried oxide (BOX) layer, for example, fully isolates the transistor channel region, such as an (N) channel region of the pixel cell from the photodiode(s) of the pixel region, eliminating the junction leakage path, thus leading to a reduction in diffusion leakage and an increase device operation speed. An increase of full well capacity can also be realized by the absence of isolation structure, such as trench isolation or isolation implant structure.

Abstract: Technology is described for mapping virtualized infrastructure resources and associated flows in a virtualized infrastructure of a service provider environment. An application dataflow involving a virtualized infrastructure resource may be described using a swim lane model. Controls within the virtualized infrastructure to enforce segmentation and security of the application dataflow may be deduced from how the application dataflow is secured into a corresponding swim lane. An infrastructure mapping service may use information that identifies virtualized infrastructure resources and describes application dataflows in the virtualized infrastructure to generate a map of the virtualized infrastructure in the form of a graph. The graph may provide a visual representation that is easy for an auditor or engineer to understand.

Abstract: A computer-implemented system includes an electromechanical device configured to be manipulated by a patient while performing an exercise session, and a processor in communication with the electromechanical device. The processor is configured to receive data, generate a map packet, and transmit the map packet. The processor is configured to use the data to generate continuity packets, where each of the continuity packets includes a contiguous portion of the data, and transmit the continuity packets. The processor is configured to use the map packet and the continuity packets to cause an output file to be generated.

Abstract: Embodiments of the present disclosure generally relate to a magnetic recording device comprising a magnetic recording head having a negative anisotropic magnetic (?Ku) material notch. The magnetic recording device comprises a main pole disposed at a media facing surface (MFS), a trailing shield disposed adjacent to the main pole, and a trailing gap disposed between the main pole and the trailing shield. The trailing shield comprises a hot seed layer disposed adjacent to the trailing gap, and a notch comprising a ?Ku material in contact with the hot seed layer and the trailing gap. The notch is disposed adjacent to a first surface of the main pole at the MFS. The notch comprising the ?Ku material results in an increased effective write magnetic field, an increased down-track field gradient due to reduced shunting from the main pole to the trailing shield, leading to an increased areal density capacity.