Patents Assigned to TECHNOLOGIES INC.
  • Patent number: 11265301
    Abstract: Technology is described for using a first key to secure communications over a network link between a server and a client. A second key may be identified. A first message may indicate the server may receive data from the client using the second key but not to transmit data to the client using the second key, and that the first key is valid for sending and receiving data between the server and the client. A second message may indicate that the client may send and receive data with the server using the second key, and that the client may receive data from the server using the first key but not transmit data to the server using the first key. A third message may indicate that the server may send and receive data with the client using the second key, and that the first key is invalid for sending and receiving data between the server and the client.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: March 1, 2022
    Assignee: AMAZON TECHNOLOGIES, INC.
    Inventors: Sanjeev Gupta, Frederick David Sinn
  • Patent number: 11262232
    Abstract: Functionality of sensors on a shelf or other inventory location is tested by encouraging an interaction and determining if the output from the sensors on the shelf is consistent with the interaction. An interaction at the shelf can include, for example, a user adding or removing an item from the shelf. To encourage this type of interaction with the shelf or items therein, an announcement may be generated and presented to a user. The announcement may comprise an advertisement with some type of incentive for the user to add or remove an item from the shelf. Upon verifying such an interaction, sensor data before and after the interaction can be compared to generate diagnostic data for the sensor, which can indicate whether the sensor is operational or malfunctioning.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: March 1, 2022
    Assignee: AMAZON TECHNOLOGIES, INC.
    Inventors: Alexander Michael McNamara, Sridhar Boyapati, Aaron Craig Thompson, David Echevarria Ignacio, David William Bettis, Korwin Jon Smith
  • Patent number: 11264345
    Abstract: A method for forming a direct hybrid bond and a device resulting from a direct hybrid bond including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, capped by a conductive barrier, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads capped by a second conductive barrier, aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads capped by conductive barriers formed by contact bonding of the first non-metallic region to the second non-metallic region.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: March 1, 2022
    Assignee: INVENSAS BONDING TECHNOLOGIES, INC.
    Inventor: Paul M. Enquist
  • Publication number: 20220057449
    Abstract: A detection circuit is configured to detect phase information between two clock signals of different frequencies, and the two clock signals include a low frequency clock signal and a high frequency clock signal. The detection circuit includes: a signal generation module, configured to detect the low frequency clock signal at an edge of the high frequency clock signal to generate a to-be-sampled signal, and generate a target sampling signal when the high frequency clock signal is kept at a preset level and the low frequency clock signal meets a preset condition; and a sampling module, connected with the signal generation module and configured to detect the to-be-sampled signal at an edge of the target sampling signal to generate a detection result signal.
    Type: Application
    Filed: August 22, 2021
    Publication date: February 24, 2022
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: KangLing JI
  • Publication number: 20220055337
    Abstract: The present disclosure concerns a flexible thermal insulation assembly to thermally insulate matter from an external environment, the flexible thermal insulation assembly comprising a plurality of thermal insulation covering sections comprising an outer layer and an insulated matter-facing layer, the plurality of thermal insulation covering sections being configurable in an adjacent configuration wherein the plurality of thermal insulation covering sections are articulately connected to one another to substantially conform to an outer surface of the insulated matter; and an insulated matter-mounting assembly securing the plurality of thermal insulation covering sections onto the insulated matter with the insulated matter-facing layers of the plurality of thermal insulation covering sections at least partially covering the insulated matter and substantially conforming thereto. The present disclosure also concerns a method for thermally insulating matter, such as a snow heap, from an external environment.
    Type: Application
    Filed: December 13, 2019
    Publication date: February 24, 2022
    Applicant: GLACIES TECHNOLOGIES INC.
    Inventors: Maxim Bergeron, Mathieu Kirouac
  • Publication number: 20220058079
    Abstract: A Fail Bit (FB) repair method includes: a bank to be repaired of a chip to be repaired is determined; first repair processing is performed on a first FB using a redundant circuit; a bit position of a second FB in each target repair bank is determined, and second repair processing is performed on the second FB; an unrepaired FB in each target repair bank is determined, and candidate repair combinations of the unrepaired FBs and a candidate combination count are determined; and if the candidate combination count is greater than a combination count threshold, a target repair position is determined, and repair processing is performed on the target repair position using a Redundant Word-Line (RWL), the target repair position being a position of an FB that maximally reduces the candidate combination count after repair processing.
    Type: Application
    Filed: August 17, 2021
    Publication date: February 24, 2022
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Yui-Lang CHEN
  • Publication number: 20220059182
    Abstract: A Fail Bit (FB) repair method and device can be applied to repairing an FB in a chip. The method includes: a bank to be repaired including multiple target repair banks in a chip to be repaired is determined; first repair processing is performed on a first FB in each target repair bank by using a redundant circuit; a second FB position determination step is executed to determine a bit position of a second FB, and second repair processing is performed on the second FB; unrepaired FBs in each target repair bank is determined, and the second FB position determination step is recursively executed to obtain a test repair position of each unrepaired FB to perform third repair processing on the unrepaired FB according to the test repair position.
    Type: Application
    Filed: September 6, 2021
    Publication date: February 24, 2022
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Yui-Lang CHEN
  • Publication number: 20220057432
    Abstract: A test fixture includes a signal test board, a circuit routing, and a branch routing. The signal test board includes a first surface and a second surface. The first surface has a first pin and a test point. The second surface has a second pin. The circuit routing is located in the signal test board and configured to connect the first pin and a corresponding second pin. A portion of the circuit routing includes an upper routing connected with one first pin, a lower routing connected with one second pin, and a via-hole routing connected with two ends of the upper routing and the lower routing. One end, connected with the via-hole routing, of the upper routing is located in a projection area of the corresponding test point. The branch routing is located in the signal test board and configured to connect the test point with a corresponding upper routing.
    Type: Application
    Filed: November 5, 2021
    Publication date: February 24, 2022
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Maosong MA, Xinwang CHEN, Zhangqin ZHOU
  • Publication number: 20220059538
    Abstract: A semiconductor device includes: a substrate, including a memory array region and a peripheral region; a first interlayer insulation layer and the second interlayer insulation layer which are formed on the substrate in the memory array region and the peripheral region, the first interlayer insulation layer and the second interlayer insulation layer being arranged at intervals along a direction perpendicular to the substrate; a columnar capacitor array, including columnar capacitors arranged at intervals, and the columnar capacitors being formed in the first interlayer insulation layer and the second interlayer insulation layer in the memory array region; and a contact structure, formed in the first interlayer insulation layer and the second interlayer insulation layer in the peripheral region.
    Type: Application
    Filed: July 27, 2021
    Publication date: February 24, 2022
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Liang ZHAO
  • Publication number: 20220059539
    Abstract: A method for preparing a semiconductor structure includes: providing a semiconductor substrate; forming a groove in the semiconductor substrate; forming a first insulation layer, the first insulation layer at least covering an inner wall of the groove; forming a channel layer, the channel layer at least covering an inner wall of the first insulation layer; forming a second insulation layer, the second insulation layer at least covering an inner wall of the channel layer; filling the groove with a word line structure; removing part of the semiconductor substrate, part of the first insulation layer, and part of the channel layer, and forming a recess region in an outer side wall of the second insulation layer; and forming a source-drain in the recess region, the source-drain being electrically connected with the channel layer.
    Type: Application
    Filed: July 30, 2021
    Publication date: February 24, 2022
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Gongyi WU, Yong LU, Longyang CHEN
  • Publication number: 20220059694
    Abstract: A manufacturing method of an integrated circuit memory includes: a substrate is provided; a bit line extending along a first direction is formed on the substrate; a word line extending along a second direction is formed on the bit line; and a vertical storage transistor is formed in an overlapping region where the word line and the bit line are spatially intersected, the vertical storage transistor being located on the bit line, and connected to the bit line.
    Type: Application
    Filed: July 30, 2021
    Publication date: February 24, 2022
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Qu LUO
  • Patent number: 11253185
    Abstract: Some embodiments include processing data via an executable file on a monitor to reduce the dimensionality of the data being transmitted over the wireless network. The output of the executable file also encrypts the data before being transmitted wireless to a remote server. The remote server receives the transmitted data and makes likelihood inferences based on the recorded data.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: February 22, 2022
    Assignee: IRHYTHM TECHNOLOGIES, INC.
    Inventors: Steven Szabados, Yuriko Tamura, Xixi Wang, George Mathew
  • Patent number: 11256224
    Abstract: Systems, methods, and software to facilitate simulating machines used in industrial automation are disclosed herein. In at least one implementation, motion of a solid model of a machine is analyzed to generate a motion profile of the solid model. An industrial controller system is then configured based on the motion profile of the solid model. A simulation of the machine controlled by the industrial controller system is executed, and motion of the simulation of the machine as controlled by the industrial controller system is analyzed. The motion of the simulation of the machine is then compared to the motion profile of the solid model to determine how closely the motion of the simulation of the machine as controlled by the industrial controller system matches the motion profile of the solid model.
    Type: Grant
    Filed: October 1, 2014
    Date of Patent: February 22, 2022
    Assignee: ROCKWELL AUTOMATION TECHNOLOGIES, INC.
    Inventors: Haithem Mansouri, Francisco Maturana, Leopoldo Paredes
  • Patent number: 11258465
    Abstract: A method and apparatus for obtaining data from a memory, estimating a probability of data values of the obtained data based on at least one of a source log-likelihood ratio and a channel log-likelihood ratio, wherein each bit in the obtained data has an associated log-likelihood ratio, determining at least one data pattern parameter for the data and performing a decoding process using the at least one data pattern parameters to determine a decoded data set.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: February 22, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Dudy David Avraham, Eran Sharon, Omer Fainzilber, Alexander Bazarsky, Stella Achtenberg
  • Patent number: 11259040
    Abstract: Devices and methods are provided for adaptive multi-pass risk-based video encoding. A device may receive a segment of video frames encoded using first encoding parameters. The device may determine a group of pixels in a first video frame of the video frames. The device may determine characteristics associated with the group of pixels and may determine, based on the characteristics and a number of pixels in the group of pixels, a score associated with the segment, wherein the score is indicative of a visibility of banding compression artifact. The device may determine, based on the score, second encoding parameters associated with encoding the segment.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: February 22, 2022
    Assignee: AMAZON TECHNOLOGIES, INC.
    Inventors: Arko Sabui, Deepthi Nandakumar
  • Patent number: 11254581
    Abstract: The present invention is a process, a method, and system for recovery and concentration of dissolved ammonium bicarbonate from a wastewater containing ammonia (NH3) using gas separation, condensation, and crystallization, each at controlled operating temperatures.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: February 22, 2022
    Assignee: BION ENVIRONMENTAL TECHNOLOGIES, INC.
    Inventors: Dominic Bassani, Morton Orentlicher, Mark M. Simon, Stephen Pagano
  • Patent number: 11257727
    Abstract: Representative implementations of techniques and devices provide seals for sealing the joints of bonded microelectronic devices as well as bonded and sealed microelectronic assemblies. Seals are disposed at joined surfaces of stacked dies and wafers to seal the joined surfaces. The seals may be disposed at an exterior periphery of the bonded microelectronic devices or disposed within the periphery using the various techniques.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: February 22, 2022
    Assignee: INVENSAS BONDING TECHNOLOGIES, INC.
    Inventors: Rajesh Katkar, Liang Wang, Cyprian Emeka Uzoh, Shaowu Huang, Guilian Gao, Ilyas Mohammed
  • Patent number: 11257499
    Abstract: Method for managing a promises management apparatus comprises automatically transcribing, using an automatic speech recognition engine, a call between a caller and an agent, based on real-time call stream of the call, wherein the caller calls the agent for resolution of a concern using the promises management apparatus. The method comprises automatically extracting, using a natural language processing engine, in real-time a promise made by the agent to the caller based on the transcript of the call, generating promises data by assigning an agent, a type, a timeline, an action, and a mode of execution to the promise, and storing the promises data in a datastore.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: February 22, 2022
    Assignee: UNIPHORE TECHNOLOGIES INC.
    Inventors: Umesh Sachdev, Samith Ramachandran
  • Patent number: 11258719
    Abstract: The subject matter described herein includes methods, systems, and computer readable media for network congestion control tuning. A method for network congestion control tuning occurs at a network congestion control tuning analyzer. The method includes receiving in-band telemetry (INT) metadata from a system under test (SUT); analyzing network information associated with one or more remote direct memory access (RDMA) transactions for determining a tuning action for adjusting a data center quantized congestion notification (DCQCN) mechanism associated with the SUT, wherein the network information includes the INT metadata and DCQCN information; and performing the tuning action for adjusting the DCQCN mechanism associated with the SUT.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: February 22, 2022
    Assignee: KEYSIGHT TECHNOLOGIES, INC.
    Inventor: Christian Paul Sommers
  • Patent number: 11257525
    Abstract: A data storage device is disclosed comprising a head actuated over a magnetic media, wherein the head comprises a laser and a near field transducer (NFT). A thermal gradient produced in the magnetic media by the NFT is periodically measured, and a failure of the NFT is predicted based on a slope of the thermal gradient measurements.
    Type: Grant
    Filed: February 16, 2021
    Date of Patent: February 22, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Sukumar Rajauria, Pierre-Olivier Jubert, Richard M. Brockie