Abstract: A self testing ROM includes an information array (10) for storing data therein and a parity array (12) for storing associated parity information for each of the data words. The data is accessed and multiplexed for input to a block code error detect circuit (30) for detecting the error and outputting an error syndrome on a bus (32). The error syndrome is input to an error correct circuit (34) for correction of the accessed data during a first pass through the error detect circuit (30). This corrected data is then input to latches (39) and (41). The latched data is then input back to the block code error detect circuit (30) during a second pass to determine if the data was corrected. If not, this indicates that there were too many errors to be corrected by the error detection algorithm. This is detected with a system error detect circuit (43) during the second pass through the block code error detect circuit (30).

Abstract: A thermostat has a cup-shaped insulating base open at one end, a pair of terminals ultrasonically secured in the bottom of the base precisely locating respective stationary contacts within the base and having portions thereof extending outside the base, a flat metal element carrying movable contacts for engaging the stationary contacts, a flat metal motion transfer element secured to the movable contact element and having an extending portion precisely located adjacent the open end of the cup-shaped base, a spring mounted in the base biasing the movable contact element to engage and interconnect the stationary contacts, a dished thermostat metal element disposed in the open end of the base and movable with snap action in response to selected temperature change to engage and move the extending portion of the motion transfer element to move the movable contact element against the spring bias to disengage the stationary contacts, a thin electrically insulating film disposed over the thermostat metal element, and

Abstract: In video computer system having a dual-port bit-mapped RAM unit incorporating a shift register, provision is made for coupling data between column lines and the shift register, and for simultaneously preventing any column line from being coupled with the random data output terminal of the RAM unit. Accordingly, this prevents two or more different data bits from appearing simultaneously from the RAM unit and causing confusion as to which is the valid signal and which is a spurious signal.

Abstract: The present invention enables improved response time in a linked cell discharge detection device by providing additional discharge paths when indicated to speed discharge of circuit nodes in a plurality of detection cells. A circuit node is periodically precharged by connection to a voltage source. This node is selectively discharged in accordance with at least one input signal. An output device connected to the circuit node generates an output indicative of the state of the charge on the circuit node. An additional discharge device which is responsive to the output device provides an additional discharge path when the output signal indicates a charge on the circuit node less than a predetermined magnitude. This additional discharge path speeds up the complete discharge of the circuit node.

Abstract: A semiconductor chip carrier system has a printed circuit board supporting a plurality of ceramic carrier packages in rows and columns; each package has a plurality of flexible electrical conductive connection pads. A plurality of pressure exerting retaining means engage columns of the ceramic packages. The ends of the retaining means are connected to the printed circuit board for retaining the flexible electrical conductive connection pads of the columns of ceramic carrier packages in electrical contact with the printed circuit board thereby eliminating the need for solder connections.

Abstract: Adjustment of operating parameters for a functional circuit is provided by fuse links (44) and (45). For a DRAM, the fuse links (44) control the various internal delays of a timing control generator (40) and fuse links (45) control the sensitivity of sense amplifiers by controlling an access control circuit (42). The sense amplifiers (14) determine the access parameters for a plurality of memory cell arrays (10) and (12). By varying the parameters of the sense amplifiers, the access parameters can be controlled by one adjustment on the central control circuitry.

Abstract: A system for performing one semiconductor manufacturing operation or sequence of operations with reduced particulate contamination. A vacuum-tight wafer carrier, which contains numerous wafers in vacuum in a sealed box, is placed into a platform inside a vacuum load lock. The platform contains slots and protruding fingers to provide accurate registration of the position of the wafer carrier. After the load lock is pumped down, the door of the wafer carrier is opened, and a transfer arm removes wafers from the wafer carrier, in any desired order, and transfers them one by one through a port into a processing chamber.

Abstract: A system for interactively generating a natural-language input interface, without any computer-skill programming work being required. The natural-language menu interface thus generated provides a menu-selection technique whereby a totally unskilled computer user, who need not even be able to type, can access a relational or hierarchical database, without any possibility of error. That is, the user addresses commands to the database system simply by selecting words from an appropriate menu of words which could legally follow in commands, so that the user inputs commands which are phrased entirely in English, and these commands cannot be misunderstood by the database system. The present invention provides an automatic interactive system whereby such an interface is constructed.

Abstract: In a video computer system having a RAM chip with a shift register connected to its serial output terminal and actuated by a first clock circuit, a second different clock circuit is included to cause the data bit in the first stage of the register to also appear at the serial output terminal of the chip. Accordingly, signals from the first clock circuit will then sequentially transfer data bits from the shift register, to the output terminal of the RAM chip, without omitting or losing a clock cycle, or a portion thereof.

Abstract: An infrared imager, wherein an array of detection devices is formed in a thin layer of HgCdTe, which is bonded to a silicon substrate containing a corresponding array of averaging capacitors with addressing and output connections, and via holes through (or bump bonding pads on) the HgCdTe are used to connect each detection device to its corresponding averaging capacitor. The signal from each detection device is repeatedly averaged into its averaging capacitor, so that the output of each pixel site is sensed as an average over a number of read cycles which provides a greatly improved signal-to-noise ratio.

Abstract: An apparatus for reactive ion etching or plasma etching wherein the wafer faces downward. The process gas is supplied through a distributor which is below the wafer and has orifices pointing away from the wafer. The vacuum (exhaust) port is below the distributor, so that there is no bulk gas flow near the face of the wafer. Preferably transport of the process gasses and their products to the face of the wafer is dominated by diffusion.

Abstract: Method for cleaning material from the outer edge of an object by applying a solvent for the material to a flat surface adjacent the edge and moving the solvent onto the edge by centrifugal force.

Abstract: The present invention provides a structure and method for fabricating that structure which provides increased capacitance over the prior art while occupying a minimum of surface area of the integrated circuit. The present invention accomplishes this by interleaving multiple capacitor plates to provide increased capacitance while occupying the same surface area as a prior art capacitor providing a fraction of the capacitance provided by the present invention. The present invention is fabricated by providing a capacitor stack which includes interleaved plates of material which may be selectively etched and which is separated by appropriate dielectric material. One portion of the stack is masked while one set of the interleave plates is etched. The etched portion of the interleave plates is filled by a suitable dielectric and a contact is made to the remaining plates. A different portion of the stack is then exposed to an etch which etches the other set of interleave plates.

Abstract: A sonar or radar permits primary distributed scatterers that are close to the sonar or radar relative to the array dimension to be rapidly and accurately located and pertinent characteristics to be estimated, such as Doppler and complex scattering strength. The region viewed is partitioned in annuli instead of in angular pie shaped slices as is normally the case for conventional sonar. This avoids the difficulty with conventional sonar or radar of distinguishing whether a scatterer is in a side lobe or the main beam an dis preferable to conventional sonars or radars in the important case of approaching multiple scatterers, e.g. robotic vehicle sensors or torpedo terminal homing on a target, because near regions may be examined in all directions prior to further regions. Computational speed is achieved by utilizing precomputation and leaving only part of the computation to be performed in real time.

Abstract: A digital lattice filter includes a Y-adder (44) and a B-adder (106). The Y-adder (44) calculates the Y-values for a linear predictive coding voice compression technique and the B-adder (106) calculates the B-values. Each of the calculated B-values output by the B-adder (106) is input to a B-stack (118) for storage therein. The B-stack (118) delays the B-values for one sample period. Multiplier constants are contained in a K-stack (90) for output to both adders (44) and (106) for use in the multiplication operation. The final value is stored in a Y1-register (104). Each of the adders (44) and (106) are multiplexed to perform a multiplication operation followed by an addition operation to generate the respective Y- and B-values. A generated Y-value is stored in a Y-register (56) for use in the next sequential Y calculation. In addition, the generated Y-value is used as a multiplicand for generation of a B-value.

Abstract: A protective circuit arrangement is described for protecting semiconductor components connected to input and output terminals (10) against overvoltages in bipolar integrated circuits. The circuit arrangement contains at least one supply voltage terminal (12) and a ground terminal (14). Between the ground terminal (14) and at least the input and output terminals (10) which are connected to components sensitive to overvoltage a thyristor-tetrode (22) having a first control electrode (28) and a second control electrode (30) is inserted, the first control electrode (28) being connected to a line (18) which in the operative state of the integrated circuit lies at a voltage above the ground potential and the second control electrode (30) being connected to the ground terminal 14.

Abstract: A computer system displays, in two dimensions, a representation of a three-dimensional volume. The three-dimensional volume representation is a tessellation of cells, represented as three-dimensional units. The three-dimensional volume is represented by a plurality of digital numbers. A designator designates which of the digital numbers are to be represented in the two-dimensional display. Each digital number is represented by one cell. Also, each digital number represents a color. Each corresponding cell is colored in accordance with the digital number. A designator designates which of the digital numbers is to be represented by a cell in the three-dimensional representation. A cursor, controlled by a mouse, may be used to indicate which of the three-dimensional volume representation is to be excavated by indicating at the appropriate cells and then electronically ordering the excavation.

Abstract: A system for visualization on a video screen (6) in a graphical mode in which the visual information to be displayed is defined on the screen by a point by point sweeping, from page memory containing, at a given time, all of the video information to be displayed, and a video display processor (4), connected to a random access memory containing said page memory and to a display control unit (37) adapted to convert the information relative to the image composed from the contents of the memory (5) to screen (6) control signals, characterized in that central processing unit (1) is connected to the video display processor (4) by means of a single bus (12) over which are transmitted, on a time shared basis, the address fields and the data fields (15) and in that it includes in addition a control and interpretation circuit (27) capable, in response to an assignment signal generated by said central processing unit, to interpret the address field as an address field per se or as a control field for the video display p

Abstract: A semiconductor dynamic memory device has an array of one-transistor cells, with row and column decode to produce a 4-bit wide input or output from the array. Single-bit data-in and data-out terminals for the device are coupled to the 4-bit array input/output in a sequential mode. The row and column addresses are latched when RAS and CAS drop, and the latched address includes the address of the starting bit within the 4-bit sequence for serial I/O. The other three bits follow as CAS is cycled. This starting address is used to set a bit in a 4-bit ring counter, which is then used to cycle through the sequence. To reduce power dissipation, the inverter stages of the ring counter are operated by pulsed clocks generated from the asynchronous memory control clocks received from the CPU.

Abstract: An infrared imager, wherein a transparent gate is separated from a very narrow bandgap semiconductor (such as HgCdTe) by a thin dielectric. The gate is biased to create a depletion well in a semiconductor, and photo-generated carriers are collected in the well. The gate voltage is sensed to measure the accumulated charge. Preferably the accumulated charge is not sensed directly from the gate, but the gate output is repeatedly averaged with another capacitor, so that the output of the imager is sensed as an average over a number of read cycles, which provides a greatly improved signal-to-noise ratio. Preferably an array of the MIS detection devices is formed in a thin layer of HgCdTe, which is bonded to a silicon substrate containing a corresponding array of the averaging capacitors with addressing and output connections, and via holes through the HgCdTe are used to connect each detection device to its corresponding averaging capacitor.