Abstract: An LPC digital lattice filter includes a full adder (44) which has one input thereof multiplexed with a multiplexer (46) and the other input thereof multiplexed by a multiplexer (50). Combination of the multiplication and addition steps with the full adder (44) results in the calculation of one of the digital filter equations. The result of each of these equations is either a Y-value or a B-value. The Y-values are stored in the output of a Y-register (78) and the B-values are stored in a nine stage B-stack (100) for delay thereof. The multiplexer (60) selects multiplicands from either the output of the one stage delay (86), from the B-stack (100) or the input excitation I. The multiplexer (46) selects addends from either the output of the B-stack (100), the output of the B-register (96) or from the multiplexers (60) or (66). The values are calculated in an interleaved sequence with a Y-value calculated and then a B-value calculated utilizing this generated Y-value.

Abstract: An electrically erasable programmable memory cell of the four transistor type in which a floating gate transistor has one end of its source to drain path coupled to the write line and the other end to the read line through a read switch. Its control gate is connected to the sense line. A tunnel device has a cathode connected to the floating gate of the floating gate transistor, and an anode through a write switch connected to the write line. The gates of both the read and write select transistors are connected to the row line. By coupling one end of the read switch to the read line rather than connecting one end of the source to drain path of the floating gate transistor to the read line for unselected cells in which the read switch is off, only the capacitance of one end of the read switch is added to the parasitic capacitance of the read line whether the floating gate of the floating gate transistor has previously been charged negatively or positively.

Abstract: Silence suppression in speech synthesis systems is achieved by detecting and processing only segments of voice activity. A segment is classified as "speech" if the energy of the signal is greater than an adaptively adjusted threshold. The adaptively adjusted threshold is preferably defined as the maximum of scaled values of two separate envelope parameters, which both track the variation in energy over the sequence of frames of speech data. One contour is a slow-rising fast-falling value, which is updated only during unvoiced speech frames, and therefore track a lower envelope of the energy contour. This parameter in effect tracks an ambiant noise level. The other parameter is a fast-rising slow-falling parameter, which is updated only during voiced speech frames, and thus tracks an upper envelope of the energy contour. (This in effect tracks the average speech level.) A nonsilent energy tracker and a silent energy tracker adjust corresponding energy values representing the energy contours.

Abstract: An automatic pin inspection apparatus and method inspects a plurality of pins that are arranged in a predetermined configuration such as parallel rows and converts the image of the pins to a digital signal for application to a computer system. The digital system is compared with a known reference stored in a memory within the digital computer system and units that do not meet specified tolerances are rejected. A conveyer mechanism ensures the automation of the process. A centering technique is implemented and compensates for the jittering due to the movement of pins to ensure proper alignment of the image prior to the comparison being made.

Abstract: The present invention provides syllable boundaries from a string of phonological linguistic unit indicia and word boundary data. The syllable boundary recognizer places a syllable boundary either at the next following word boundary or prior to the second vowel phonological linguistic unit indicia following the prior syllable boundary based upon the sequence of consonant phonological linguistic unit indicia prior to that second vowel. A permitted syllable initial consonant cluster includes an optional fricative consonant, an optional stop consonant and an optional sonorant consonant. The syllable boundary recognizer searches backward from the second vowel phonological linguistic unit indicia until the permitted sequence is violated, whereupon a syllable boundary is inserted. In the preferred embodiment, a refinement permits certain strong vowel phonological linguistic unit indicia to "capture" the following phonological linguistic unit indicia and shift the syllable boundary.

Abstract: A dual detector spectroscopic endpoint determination system is used which has dual channels that enables the combination of channels to increase gain, cancel out background noise, and to use either one or more spectroscopic channels.

Abstract: A single-chip microprocessor device of the MOS/LSI type contains an ALU, several interal busses, a number of address/data registers, and an instruction register with associated control decode or microcontrol generator circuitry. The device communicates with external memory and peripherals by a bidirectional multiplexed address/data bus and a number of control lines. The ALU, registers and busses along with the control ROM are constructed in an interrelated layout whereby minimum space is needed on the chip. Like bits in all registers and the ALU are aligned and in a regular pattern. The busses are metal lines overlying each of the strips of ALU/register bits. Controls are polysilicon lines perpendicular to the busses and aligned with columns of the control ROM. The control ROM is an array of rows and columns of potential MOS transistors, compressed by eliminating column lines which contain no transistors.

Abstract: A bonding apparatus for bonding lead wires to a semiconductor surface includes a supply spool that contains a supply of the bonding wire that is fed to a capillary that is made of a non-conductive material. An electric arc forms a ball on the tip of the arc and the ball is retracted into the capillary. The ball is heated and compressed onto the semiconductor substrate and is then stitched over to a second bonding point which in most applications is the interface pin of the semiconductor device. The capillary has a non-conductive end that prevents coating of the capillary tip with the molten metal that results from the arcing of the bonding wire.

Abstract: The disclosure relates to a monolithic circuit and method of making same which includes the use of two substrates of different semiconductor materials or two substrates of the same semiconductor material wherein the processing steps required for certain parts of the circuit are incompatible with the processing steps required for other parts of the circuit.

Abstract: A programmable read-only-memory (PROM) element is disclosed in which an N-type epitaxial layer, grown on a P-type substrate with an N+ buried layer therebetween, has a P-type anode region formed in a surface portion thereof. An N-type poly-silicon layer is formed on the surface of the anode region, generally within an aperture in an insulating layer, with the dopant of the poly-silicon layer being diffused downwardly into the anode region to form a shallow N-type cathode region. A metal layer is deposited on the surface of the poly-silicon layer over the anode region, and a low resistivity path is provided to the buried layer. To program the memory element, a positive potential is applied to the metal layer relative to the buried layer to break down the barrier between the cathode and anode regions. As the reverse current flow heats the poly-silicon, the metal alloys through the poly-silicon and the cathode region, and shorts to the anode region.

Abstract: A decoder and driver circuit for producing an output voltage exceeding the power supply uses a CMOS decode circuit followed by NMOS output stage and pump circuit. The pump clock is derived from a controlled oscillator, and the oscillator is synchronized with the access cycle of the memory device in which the circuit is used, so retention of the high level output is assured for an indefinitely long cycle time.

Abstract: An input protection circuit for an MOS device uses a thick-oxide transistor connected as a diode between a metal bonding pad and ground. The channel width of this transistor is chosen to be sufficient to withstand large, short-duration current spikes caused by electrostatic discharge. More important, the spacing between a metal-to-silicon contact to the drain of this transistor and the channel of the transistor (where heat is generated), is chosen to be much larger than usual so the metal of the contact will not be melted by heat propagating along the silicon surface during the current spike due to ESD. This spacing feature also applies to circuits for output pads, or circuits using diode protection devices.

Abstract: A tilt and height adjustable display stand has a display mechanism connected to a base through a series of interconnecting linkage arms. A tilt gas spring and a height gas spring are interconnected within the linkage in such a manner as to offset the weight of the display mechanism when the display mechanism is tilted or moved vertically.

Abstract: A video system controller allows for the transfer of data between a display memory and a microprocessor that is used to control the controller and from the display memory to a CRT monitor. The transfer operations are controlled by the video system controller through a state machine that is configured with a plurality of standard cells connected in cascade arrangement, which can be configured as either a Moore or a Mealy state machine. Each state machine has a programmable logic array in which timing signals, when applied thereto, will cause a predetermined output to appear on the output on each of the standard cells. A logic means, depending upon whether the machine is a Moore type state machine or a Mealy type state machine logically manipulates the output of the programmable logic array to obtain the state output for that particular cell.

Abstract: A plasma dry etch process for etching deep trenches in single crystal silicon material with controlled wall profile, for trench capacitors or trench isolation structures. HCl is used as an etchant under RIE conditions with a SiO.sub.2 hard mask. The SiO.sub.2 hard mask is forward sputtered during the course of the Si etch so as to slowly deposit SiO.sub.x (x<2) on the sidewalls of the silicon trench. Since the sidewall deposit shadows etching at the bottom of the trench near the sidewall, the effect of this gradual buildup is to produce a positively sloped trench sidewall without "grooving" the bottom of the trench, and without linewidth loss. This process avoids the prior art problems of mask undercut, which generates voids during subsequent refill processing, and grooving at the bottom of the trench, which is exceedingly deleterious to thin capacitor dielectric integrity.

Abstract: A cap oxide (or oxide/nitride) prevents silicon outdiffusion during the reaction step which forms direct-react titanium silicide.

Abstract: A current source MOSFET is fabricated by forming a trench (36) in an n++ drain (source) region (32) and extending below the trench (36). A gate oxide layer (40) is disposed on the sidewalls of the trench (36) and a conductive region (38) formed in the bottom of the trench (36). A gate-to-source (gate-to-drain) contact (49) is then formed in the trench (36) and then a drain (source) contact (58) formed. The vertical gate structure defines a vertical channel region on all sides of the trench (36) to allow a wider devive to be fabricated in a smaller overall silicon area.

Abstract: A redundant column circuit includes a row shared predecoder (12) and predecoders (16), (18) and (20). The predecoders (16-20) are input to a one-of-sixty-four decoder (28) for providing sixty-four decoded outputs therefrom, each of which is input to a one-of-four multiplexer (30). Each of the multiplexers (30) selects one of four normal decode outputs and one of four redundant decode outputs. The selected decode output is determined by the four outputs from the row shared predecoder (12). A switch bank (32) of single pole double throw switches selects between a normal and a redundant output with the redundant output having the address associated therewith incremented by one. The output of the switches in the bank (32) is input to the deactivation circuits (36) for output therefrom to a memory array (38). The memory array (38) has a redundant column (R) in parallel therewith which is controlled by the first switch in the switch bank (32).

Abstract: The disclosure relates to a method of making solar cell arrays and modules and the arrays and modules wherein the arrays are formed of semiconductor spheres of P-type interior having an N-type skin housed in a pair of aluminum foil members which form the contacts to the P-type and N-type regions. The foils are electrically insulated from each other and are flexible. Multiple arrays can be interconnected to form a module of solar cell elements for converting light energy into electrical energy.

Abstract: A four position interlacing apparatus includes an interlace mirror of electromagnetic material, and an interlace mirror support member of magnetic material having a faceted surface for supporting the interlace mirror. The supporting surface has a centrally disposed ridge from which a pair of downwardly sloping facets extend at first preselected interlace angles to form ridges with a pair of downwardly sloping facets extending therefrom at second preselected interlace angles, and a corresponding plurality of bars of non-magnetic material for dividing each facet between the ridges to form a plurality of magnetic core members. Each bar of non-magnetic material extending vertically downward to aperture forming walls of the support member, said support member having solid reel bars formed in the apertures with a plurality of coils surrounding the reel bars.