Abstract: A sealed thermostatic electric switch has a heat responsive thermostatic element disposed in good heat transfer relationship with the closed end of a heat conductive cup shaped member. The side wall of the cup shaped member extends upwardly from the closed end and is spaced a selected distance from the housing of the switch. A plastic sleeve has one end tightly received over the side wall and adhesively secured thereto and another end closed except for a tubular portion extending therefrom with electrical leads of the switch extending from the switch through and beyond the tubular portion. The tubular portion has opposed wall portions which are in contact and coalesced with each other and with the aligned plastic insulation of the leads to effectively seal the tubular portion of the sleeve.A mounting plate is welded to the bottom outer surface of the cup shaped member which interfits with a strap or clip for attachment to a surface whose temperature is to be monitored.

Abstract: An optically activated keyboard provides inputs to a digital computer or the like. The keyboard includes a key housing having formed therein a wave guide matrix of intersecting columns and rows with light emitting diodes (LED's) installed in one end of each column and photo transistors installed in one end of each row. A plurality of keys are mounted at the top surface of the housing, each key having a plunger which projects through a corresponding aperture in the housing, when the key is depressed. The intersections of the columns and rows are located directly beneath the apertures so that when a key is depressed, its plunger intrudes into the volume at the intersection. Each plunger, in concert with the wave guide intersection, forms a light polarizing system. In the preferred embodiment, each plunger has a reflecting face that is angled to reflect light from the LED in the corresponding column into the corresponding row, finally impinging against the appropriate photo transistor.

Abstract: A metal-insulator-semiconductor field effect transistor using an undoped AlGaAs layer as an insulator over an n-type GaAs channel. The high breakdown field of the wide-bandgap AlGaAs results in a very high gate breakdown voltage and a low prebreakdown gate leakage current. The presence of the gate insulator also reduces the gate capacitance, Cgs. Moreover, the electron density in the channel is not all concentrated next to the heterojunction, which means that the series resistance of the channel is low, and also means that channel mobility will not be degraded by a less-than-perfect interface at the heterojunction.

Abstract: In a computer system, an improved memory circuit is provided for accomodating video display circuits with CRT screens having different resolutions. The memory circuit includes a bit-mapped RAM unit or chip having sufficient cells to accomodate any CRT screen intended to be used, and it further includes a serial shift register having a plurality of taps at locations corresponding to different preselected columns of cells in the chip. In the system, provision is included for selecting taps to unload only the portion of the shift register containing the bits of interest, whereby unused portions of the chip may be effectively excluded and the time for transferring data of interest to the CRT screen is reduced.

Abstract: In accordance with a broad aspect of the invention, a system is presented for parametrically and functionally testing integrated circuit devices in parallel. At least one integrated circuit device receiving channel is provided for defining a plurality of integrated circuit device test stations therealong, and means are provided for delivering parametric and functional test signals at least functionally in parallel to each of the integrated circuit device test stations. Means are provided at each test station for selectively engaging the integrated circuit devices to apply the parametric and functional test signals to the integrated circuit device at that station, and to selectively isolate the device from the test signals. Means are provided for receiving an output from each test location in response to the test signals, and means for determining from the output the parameters of each tested integrated circuit device.

Abstract: The present invention is manner of synchronization in a video overlay system for overlay of an internal video signal upon an external video signal. In the video overlay system of the present invention the horizontal synchronization pulses of the external video signal are detected to enable generation of the internal video signal having synchronized horizontal lines. This is achieved by generating a video clock signal for control of video signal generation at a frequency that is a multiple of the frequency of the horizontal lines of the external video signal. The vertical synchronization signal of the external video signal is detected in the preferred embodiment to enable generation of the internal video signal having video frames in synchronism with those of the external video signal.

Abstract: A pressure responsive device suitable for high pressure hydraulic applications has a formed metal disc or diaphragm adapted to move from an original dished configuration toward an inverted dished configuration with snap action in response to the application of a selected fluid pressure. Support means of selected surface radius extend into the space defined by the original dished configuration of the diaphragm to intercept and limit such diaphragm movement to prevent damage to the diaphragm under the applied pressure and to limit stresses in the diaphragm material particularly adjacent to the periphery of the dished part of the diaphragm for improving reliability and service life of the device.

Abstract: A microprocessor system includes a CPU device with on-chip or off-chip memory, and data and control busses for accessing memory and/or peripherals. The peripheral circuitry includes one or more channels for input and/or output of data, wherein various characteristics of the treatment of data in the channel are controlled by the program being executed in the CPU. In one embodiment analog input and output channels are included, and the A-to-D or D-to-A conversion rates are selected by executing a data output instruction by the CPU. The cut-off points of the filters are likewise selected. The A-to-D converter loads a first-in first-out memory which is read by the CPU in burst mode when filled. Likewise, the CPU loads digital data to a first-in first-out memory in the output channel, and then the D-to-A converts at its selected rate.

Abstract: In one embodiment of the present invention, silicon spheres are fabricated by applying a slurry of metallurgical grade silicon, or other suitable material, on the surface of a substrate capable of maintaining integrity beyond the melting point of silicon. The layer of metallurgical grade silicon is then patterned to provide regions of metallurgical grade silicon of uniform size. The substrate and metallurgical grade silicon are then heated beyond the melting point of silicon. The metallurgical grade silicon then beads to the surface as relatively pure silicon and forms silicon spheres due to the high cohesion of silicon. The structure is then cooled below the melting point of silicon and the silicon spheres then crystallize. The silicon spheres are then removed from the surface of the substrate and are further processed using techniques disclosed in copending U.S. patent application Ser. Nos. 647,551 and 647,578 to further purify the crystalline silicon spheres.

Abstract: The spatial light modulator drive system of the present invention permits useful light modulation, such as employed in a projection display device, with a minimum of required data input. A plurality of charge storage cells with associated charge dependent light modulator cells are disposed at the intersection of row and column conductors. The drive system alternately refreshes the data stored in a particular row and responds to external commands. The automatic refresh involves selecting a particular row via a dedicated refresh counter, reading the column data in that row, storing this data in a column latch and rewriting this data to the same row. The generation of a new display is achieved in a number of steps. A particular row is selected by externally applied data. The data type, such as number of bits and variations in shade, is also specified.

Abstract: A CMOS driver circuit for producing a high-level voltage, exceeding the voltage supply, uses an inverter and an output stage. The inverter circuit is supplied from the usual voltage supply for the chip, and this inverter is followed by the output stage which is supplied from an on-chip generator producing a higher level voltage. The current requirement of the on-chip generator is kept to a minimum by charging the output capacitance mainly from the voltage supply, and using the output stage only for the latter part of a charging cycle.

Abstract: A self-tuning controller, for dynamic control of the servo valve and the actuator (mass, column, pad) of a seismic source vibrator, includes a state variable feedback network associated with a model reference for the servo valve and the actuator. The model references provide controllable states of the servo valve and actuator that would otherwise be inaccessible. The models run on-line and have the same inputs as the servo valve and the actuator. A Kalman filter provides a full order observer that compares accessible states between each model and the servo valve and actuator, and updates the model states in dependence on the difference.

Abstract: A semiconductor dynamic memory device contains differential sense amplifiers for detecting the charge on bit line halves which are of the folded type. The sense amplifiers are multiplexed so that one of two opposite pairs of bit line halves are selected. The two opposite pairs share precharge and active pull-up circuits on one side of the array, and share column output lines on the opposite side. Thus, the multiplex circuitry operates not only for selecting one side or the other for sensing, but also for coupling precharge and boost voltages or read/write data back and forth from one side of the sense amplifier to the other. The active pull-up circuits are activated in both read and write portions of a read-modify-write cycle.

Abstract: A low temperature, low encroachment isolation technique using differential oxidation results in an isolated semiconductor body having an N+ substrate (12) and an N epi layer (14) forming a mesa. N+ implants (22a) and (22b) are implanted on opposite sides of the mesa. Oxide is grown over the surface of the device with differential oxidation thus resulting in thick regions (24) over the N+ dopant regions and a thin region (26) over the undopant mesa region.

Abstract: The present invention is a low cost electronic apparatus construction method which may be employed for hand held calculators, electronic learning aids and electronic games. This technique involves a simplification in the construction of the apparatus including reduction in the number of piece parts necessary for the assembly. The primary electrical circuit interconnection pattern of the electronic apparatus is printed upon a part of the case of the apparatus which must be nonconducting. This printed circuit pattern together with the construction of the back case includes connection portions for electrical connection to the major components of the apparatus which may include an integrated circuit, a display device and an electrical power source. The primary circuit pattern printed on the back case includes a plurality of interleaved comb key switch positions.

Abstract: A -CMOS clock generator circuit is controlled by two clocks, one always going high before the other when entering an active cycle, and always going low before the other in entering a precharge cycle; this one clock precharges a capacitor through a P-channel transistor, and holds a drive node discharged. Two sets of semi-connected N-channel output transistors are used, with the gates of the top two driven by the drive node, and the gates of the bottom two driven by a CMOS inverter which has the second clock as its input. The inverter output also drives the gate of a P-channel transistor between the capacitor and the drive node. Another P-channel transistor with the first clock on its gate couples the drive node to the intermediate node of the first output pair. The second clock transfers the charge from the capacitor to the drive node, which also causes the capacitor to boot the drive node above the supply. When the first clock goes low it discharges the booted node to the supply rather than to ground.

Abstract: A transport mechanism (40) for transporting a semiconductor slice cassette between a clean carrier (10) and a process machine comprises a housing (41) having a forward portion (42) positioned in the people-occupied area of the clean room and a rear portion (46) positioned in the process machine area aerodynamically isolated from people. A moveable glider plate (50) is adapted to receive the carrier (10) and is initially positioned in an aperture provided in the upper surface of forward portion (42). A gearing mechanism (54) is provided which cooperates with glider plate (50) to move the semiconductor slice cassettes mounted on the base of carrier (10) between forward portion (42) and rear portion (46).

Abstract: A circuit for inhibiting data transfer to addressed memory locations in a plurality of arrays on a semiconductor chip includes an arbitration circuit (68) that distinguishes between separate inhibit signal inputs on dedicated CAS terminals and multiplexed inhibit signals on the input of an I/O buffer (66). The arbitration circuit (68) controls the enable circuits (64) for transferring data from the I/O buffer (66) to memory arrays (10), (12), (14) and (16). Separate inhibit signals allow multiple arrays to share common row and column decoders and maintain separate read/write capability.

Abstract: A sense amplifier circuit for a CMOS DRAM or the like uses cross-coupled P-channel load transistors and cross-coupled N-channel driver transistors. Both of the P-channel transistors are in an N-well in the center of a symmetrical layout on the chip. Each N-channel transistor is split into two separate transistors, one on each side of the N-well, so that a balanced configuration is possible.

Abstract: A hermetically sealed, creep acting pressure switch has a sensor assembly comprising a bulged metallic membrane welded between a port fitting and a support. A switch assembly, attached to the sensor assembly, includes a housing which has a switch chamber in which, in one embodiment, a pair of stationary contacts are mounted. A piston having a force receiving surface at one end is biased into engagement with the membrane with an adjustable calibrated force. An electrically conductive contact bridge is mounted on and is movable with the piston. The switch can be normally open or normally closed depending on which side of the contact bridge the stationary contacts are mounted. In an alternate embodiment a miniature switch is mounted in the switch chamber and is adapted to be actuated by the piston.