Patents Assigned to Texas Instruments
  • Communication on a pilot wire
    Patent number: 8831077
    Abstract: Systems and methods are disclosed for communicating on a pilot wire between Electric Vehicle Service Equipment (EVSE) and an Electric Vehicle (EV). The EVSE and EV exchange a Pulse Width Modulation (PWM) signal on the pilot wire to control charging operations of the EV. Data communications may also be transmitted on the pilot wire, such as between transmit and receive modems. The modems transmit communication signals either continuously, without regard to the state of the PWM signal, or only when the PWM is in an off-state. If transmitting while PWM is on, the modem needs a large coupling impedance and/or a large signal injection. To transmit only when the PWM is off, the modem may use a blocking diode in the coupling circuit or may synchronize to the pulses in the PWM signal.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: September 9, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Badri Varadarajan, Il Han Kim, Anand Dabak, Edward Mullins
  • Shuttle plate having pockets for accomodating multiple semiconductor package sizes
    Patent number: 8829939
    Abstract: An input/output shuttle plate includes a metal plate having a plurality of pockets. The plurality of pockets have a bottom, a sidewall portion and a pocket depth. A first seating surface at a first pocket depth (d3) is for supporting a first packaged semiconductor device having a first package size, and at least a second seating surface at a second pocket depth (d4) is for supporting a second packaged semiconductor device having a second package size. The first pocket depth is less than the second pocket depth (d3<d4), and the first package size is larger than the second package size. The shuttle plate is adapted to be fit on a test handler, such as by shuttle plate clips.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: September 9, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Mhark Lester Lauron Ponghon, Jose Karlo Garzon Tafalla, Rossbert Galvez Arguelles, Archie Gil Flores Quevedo, Christian Malunes Quidato, Allen Harvey Salazar Bata-Anon
  • Ultrashallow emitter formation using ALD and high temperature short time annealing
    Patent number: 8828835
    Abstract: An integrated circuit containing a bipolar transistor including an emitter diffused region with a peak doping density higher than 1ยท1020 atoms/cm3, and an emitter-base junction less than 40 nanometers deep in a base layer. A process of forming the bipolar transistor, which includes forming an emitter dopant atom layer between a base layer and an emitter layer, followed by a flash or laser anneal step to diffuse dopant atoms from the emitter dopant atom layer into the base layer.
    Type: Grant
    Filed: March 5, 2010
    Date of Patent: September 9, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Rick L. Wise, Hiroshi Yasuda
  • Negative edge preset reset flip-flop with dual-port slave latch
    Patent number: 8829963
    Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. Clock signals CKT and CLKZ and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CKT and CLKN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, SS, SSN RE, and PREN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: September 9, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Steven Bartling, Sudhanshu Khanna
  • Floating point multiplier circuit with optimized rounding calculation
    Patent number: 8832166
    Abstract: An optimized floating point multiplier rounding circuit that minimizes the increase of the critical timing path of the calculation. The values of the temporary mantissa required to make the rounding decision are calculated simultaneously by the circuit shown in the invention.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: September 9, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Timothy David Anderson
  • Mapping schemes for secondary synchronization signal scrambling
    Patent number: 8830984
    Abstract: Embodiments of the present disclosure provide a transmitter, a receiver and methods of operating a transmitter and a receiver. In one embodiment, the transmitter includes a synchronization unit configured to provide a primary synchronization signal and a secondary synchronization signal having first and second segments. The transmitter also includes a secondary scrambling unit configured to provide a scrambled secondary synchronization signal, wherein scrambling agents for the first and second segments are derived from a primary synchronization sequence of the primary synchronization signal. The secondary scrambling unit is further configured to provide an additional scrambling of one of the first and second segments, wherein a second scrambling agent is derived from the remaining segment of a secondary synchronization sequence of the secondary synchronization signal.
    Type: Grant
    Filed: April 2, 2012
    Date of Patent: September 9, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Anand G. Dabak, Eko N. Onggosanusi, Badri Varadarajan
  • Low power all digital PLL architecture
    Patent number: 8830001
    Abstract: A new all digital PLL (ADPLL) circuit and architecture and the corresponding method of implementation are provided. The ADPLL processes an integer and a fractional part of the phase signal separately, and achieves power reduction by disabling circuitry along the integer processing path of the circuit when the ADPLL loop is in a locked state. The integer processing path is automatically enabled when the loop is not in lock. Additional power savings is achieved by running the ADPLL on the lower-frequency master system clock, which also has the effect of reducing spur levels on the signals.
    Type: Grant
    Filed: June 5, 2008
    Date of Patent: September 9, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Jingcheng Zhuang, Robert Bogdan Staszewski
  • Dynamic data trace output scheme
    Patent number: 8832318
    Abstract: Data streams are generated for tracing target processor activity. When multiple streams are on, they are written at different times into their individual FIFO. It is possible that for a specific stream, the length and fields of the data that should be exported vary. This invention is a scheme to send out only the relevant fields.
    Type: Grant
    Filed: November 28, 2006
    Date of Patent: September 9, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Manisha Agarwala, Maria B. H. Gill, John M. Johnsen
  • Keep alive message overhead reduction for communication networks
    Patent number: 8830868
    Abstract: A method of communications in a network having plurality of nodes including a base node (BN) and a plurality of levels (i) each including at least one service node (SN). The number (Ni(t)) of SNs registered in each of a plurality of i are determined. The current Keep Alive timer out (KA_TO) value for a KA timer at the BN is dynamically adjusted to an updated KA_TO value based on Ni(t) and i. Dynamically adjusting KA_TO values reduces the KA message overhead the network compared to known KA_TO value implementations.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: September 9, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Ramanuja Vedantham, Kumaran Vijayasankar, Ram Krishnan
  • Method, system and computer program product for identifying locations of detected objects
    Patent number: 8831337
    Abstract: First and second objects are detected within an image. The first object includes first pixel columns, and the second object includes second pixel columns. A rightmost one of the first pixel columns is adjacent to a leftmost one of the second pixel columns. A first equation is fitted to respective depths of the first pixel columns, and a first depth is computed of the rightmost one of the first pixel columns in response to the first equation. A second equation is fitted to respective depths of the second pixel columns, and a second depth is computed of the leftmost one of the second pixel columns in response to the second equation. The first and second objects are merged in response to the first and second depths being sufficiently similar to one another, and in response to the first and second equations being sufficiently similar to one another.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: September 9, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Peter Barnum
  • Field oriented control of a motor with a single shunt
    Patent number: 8829846
    Abstract: A method for driving a motor is provided. Pulse width modulation (PWM) signals are generated from a voltage signal and a commanded angle signal, which drives a motor with multiple phases. A motor current from a motor is measured with a single shunt and converted into a digital signal. Based on the digital signal and the commanded angle signal, direct-axis and quadrant-axis currents for the motor can be determined, and the voltage signal and the commanded angle signal can be adjusted based at least in part on the direct-axis and quadrant-axis currents.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: September 9, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Ling Qin
  • Superframe coordination in beacon-enabled networks
    Patent number: 8830980
    Abstract: Systems and methods for designing, using, and/or implementing superframe coordination in beacon-enabled networks are described. In various implementations, these systems and methods may be applicable to Power Line Communications (PLC). For example, a method may include implementing a Media Access Control (MAC) superframe using a communication device. The MAC superframe may include a plurality of beacon slots, a plurality of Contention Access Period (CAP) slots following the plurality of beacon slots, a Contention Free Period (CFP) poll access slot following the plurality of CAP slots, a CFP slot following the CFP poll access slot, an inactivity period following the CFP slot, a beacon region following the inactivity period, and a communication slot following the beacon region. The method may also include communicating with another communication device using the MAC superframe.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: September 9, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Kumaran Vijayasankar, Ramanuja Vedantham, Badri N. Varadarajan, Anand G. Dabak
  • Method of forming an integrated circuit package including a direct connect pad, a blind via, and a bond pad electrically coupled to the direct connect pad
    Patent number: 8828799
    Abstract: A method for forming an integrated circuit package is disclosed. A flex circuit is form by forming a direct connect pad on a first side of a dielectric layer. After forming the direct connect pad, an opening from a second side of the dielectric layer is formed to expose the direct connect pad. A blind via is formed within the opening in the dielectric layer. A first conductor is formed within the opening. A bond pad of a semiconductor die is electrically coupled with the direct connect pad using a second conductor, wherein the bond pad and the second conductor directly overlie the direct connect pad.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: September 9, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Kenneth Robert Rhyner, Peter R. Harper
  • ESD protection using diode-isolated gate-grounded NMOS with diode string
    Patent number: 8829618
    Abstract: An ESD protection circuit with a diode string coupled to a diode-isolated, gate-grounded NMOS ESD device. A method of forming an ESD protection circuit with a diode string coupled to a diode-isolated, gate-grounded NMOS ESD device.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: September 9, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Ponnarith Pok, Kyle Schulmeyer, Roger A. Cline, Charvaka Duvvury
  • Method of substantially reducing the formation of SiGe abnormal growths on polycrystalline electrodes for strained channel PMOS transistors
    Patent number: 8828825
    Abstract: The likelihood of forming silicon germanium abnormal growths, which can be undesirably formed on the gate electrode of a strained-channel PMOS transistor at the same time that silicon germanium source and drain regions are formed, is substantially reduced by using protection materials that reduce the likelihood that the gate electrode is exposed during the formation of the silicon germanium source and drain regions.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: September 9, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Hiroaki Niimi, James Joseph Chambers
  • Digital time-interleaved RF-PWM transmitter
    Patent number: 8831085
    Abstract: A method for transmitting radio frequency (RF) signals is provided. In-phase (I) and quadrature (Q) signals are received and filtered using sigma-delta modulation. I and Q pulse width modulation signals are generated from the filtered I and Q signals and interleaved so as to generate a time-interleaved signal. The time-interleaved signal is then amplified to generate the RF signals.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: September 9, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Rahmi Hezar, Lei Ding, Joonhoi Hur, Baher S. Haroun
  • Intentional idle gaps in coexisting wireless networks
    Patent number: 8830929
    Abstract: A wireless combination device includes a first wireless transceiver configured for communication via a first wireless network over a first band, and a second wireless transceiver configured for communication via a second wireless network over a second band that overlaps the second band. The combination device includes a medium allocation scheduler coupled to the first wireless transceiver and second wireless transceiver for implementing spaced-mode operation that intentionally inserts idle gaps in transmissions via the second wireless network when triggered by the presence of at least one spaced-mode triggering condition. The idle gaps allow wireless transmissions via the first wireless network to be received by the combination device with higher probability, and without the need for clear to send (C2S) protection.
    Type: Grant
    Filed: June 15, 2011
    Date of Patent: September 9, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Yanjun Sun, Ariton E. Xhafa, Ramanuja Vedantham, Xiaolin Lu
  • Stepped dielectric for field plate formation
    Patent number: 8829613
    Abstract: A semiconductor device is formed with a stepped field plate over at least three sequential regions in which a total dielectric thickness under the stepped field plate is at least 10 percent thicker in each region compared to the preceding region. The total dielectric thickness in each region is uniform. The stepped field plate is formed over at least two dielectric layers, of which at least all but one dielectric layer is patterned so that at least a portion of a patterned dielectric layer is removed in one or more regions of the stepped field plate.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: September 9, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Sameer Pendharkar, Naveen Tipirneni
  • Cell based temperature monitoring
    Patent number: 8831904
    Abstract: A system and method for measuring a temperature in at least one energy storage unit. They system includes at least one temperature sensor thermally coupled to the at least one energy storage unit, and a battery management controller in communication with the at least one temperature sensor. The battery management controller is configured to process a temperature of the at least one energy storage unit to obtain an internal temperature in the at least one energy storage unit.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: September 9, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: John Houldsworth
  • System for controlling SiGe-to-gate spacing
    Patent number: 8828833
    Abstract: A method of forming PMOS transistors. A SiGe cavity formation process includes cavity etching a structure including a gate stack having a gate electrode on a gate dielectric on a substrate, a sidewall spacer, and a hardmask layer on the gate electrode. The cavity etching includes (i) a first anisotropic dry etch for etching through the hardmask layer lateral to the gate stack and beginning a recessed cavity in the substrate, (ii) a dry lateral etch, and (iii) a second anisotropic dry etch. A wet crystallographic etch completes formation of the recessed cavity. A customized time is calculated for a selected dry etch step from the plurality of dry etch steps based on in-process SiGe cavity data for a measured cavity parameter for a SiGe cavity formation process. The customized time for the selected dry etch is used to cavity etch at least one substrate in a lot or run.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: September 9, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: James Walter Blatchford, Chet Vernon Lenox