Abstract: A capacitive sensing system includes a controller, a node connected to one side of a capacitance, the controller configured to measure the capacitance by measuring a time for a voltage across the capacitance to reach a predetermined reference voltage, and the controller causing the time period for capacitance measurements to vary even when the capacitance is constant.

Abstract: A method of making an integrated circuit module starts with a top leadframe strip comprising a plurality of integrally connected top leadframes. A plurality of flipchip dies are mounted on the top leadframe strip with solder bumps of each flipchip bonded to predetermined pad portions on each of the top leadframes. The top leadframe strip is attached to a bottom leadframe strip. The bottom leadframe strip has a plurality of integrally connected bottom leadframes each having a central die attach pad (DAP) portion and a peripheral frame portion. A back face of each flipchip die contacts the DAP portion of each bottom leadframe. Lead portions of each top leadframe are attached to the peripheral frame portion of each bottom leadframe. The top leadframe strip is attached to the bottom leadframe strip with a back face of each flipchip die contacting the DAP portion of each bottom leadframe and with lead portions of each top leadframe attached to the peripheral frame portion of each bottom leadframe.

Abstract: A system on chip (SoC) provides a memory array of self referencing nonvolatile bitcells. Each bit cell includes two ferroelectric capacitors connected in series between a first plate line and a second plate line, such that a node Q is formed between the two ferroelectric capacitors. The first plate line and the second plate line are configured to provide a voltage approximately equal to first voltage while the bit cell is not being accessed. A clamping circuit coupled to the node Q. A first read capacitor is coupled to the bit line via a transfer device controlled by a first control signal. A second read capacitor coupled to the bit line via another transfer device controlled by a second control signal. A sense amp is coupled between the first read capacitor and the second read capacitor.

Abstract: An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.

Abstract: A method of assembling semiconductor devices includes applying a metal paste including a plurality of metal particles having an average size less than 50 nanometers and a binder material onto a metal terminal of a package substrate. The metal paste is processed including a heat up step in a reducing gas atmosphere and then a vacuum sintering step at a temperature of at least 200° C. for forming a sintered metal coating. A semiconductor die is attached onto a die attach area of the package substrate. A bond wire is then connected between a bond pad on the semiconductor die and the sintered metal coating on the metal terminal.

Abstract: An electronic device for switched DC-DC conversion of an input voltage level into an output voltage level, comprising a first power switch and a second power switch, being connected in parallel and having a different gate width, and a driving stage that is configured to selectively drive the first power switch and/or second power switch depending on a load current output.

Abstract: A method is provided that includes generating coefficients of a scene adaptive filter (SAF) based on differences between values of neighboring pixels in a representative two dimensional (2D) image, and applying the SAF to a plurality of corresponding 2D images.

Abstract: In a video encoder, pixel values of a macro-block are processed to determine an activity measure indicative of the type of content in the macro-block. Several techniques are employed for determining the activity measure of a macro-block. In an embodiment, a default quantization scale for quantizing a macro-block is modified based on the activity measure of the macro-block. In another embodiment, the macro-block is classified into one of multiple classes based on its activity measure. The default quantization scale for quantizing the macro-block is modified based on the classification of the macro-block. In yet another embodiment, an encoding mode to be used for encoding a macro-block is also determined on the basis of the class of the macro-block. Several of the techniques exploit the fact that the human visual system (HVS) has different sensitivities in perceiving a (rendered) macro-block or video frame, depending on the type of macro-block content.

Abstract: A method for forming bond pads on a semiconductor die includes forming a dielectric stack including a bottom and top dielectric layer having a contact hole therethrough over a bond pad. An outer edge of the bottom dielectric layer within the contact hole extends beyond an outer edge of the top dielectric layer to define a bond pad edge. A second metal layer on a first metal layer is deposited. A first photoresist layer is formed exclusively within the contact hole. The second metal layer is wet etched to recess the second metal layer from sidewalls of the bottom dielectric layer in the contact hole. A second photoresist layer is formed exclusively within the contact hole. The first metal layer is wet etched to recess the first metal layer from the top dielectric layer. The first metal layer extends over the bond pad edge onto the bottom dielectric layer.

Abstract: Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication circuits have data inputs, data outputs, a clock input for timing or synchronizing the data input and/or output communication, and a mode input for controlling the data input and/or output communication. A clock/mode signal connects to the clock input of one circuit and to the mode input of the other circuit. A mode/clock signal connects to the mode input of the one circuit and to the clock input of the other circuit. The role of the mode and clock signals on the mode/clock and clock/mode signals, or their reversal, selects one or the other of the data communication circuits.

Abstract: In a SOI process, a high lateral voltage isolation structure is formed by providing at least two concentric dielectric filled trenches, removing the semiconductor material between the dielectric filled trenches and filling the resultant gap with dielectric material to define a single wide dielectric filled trench.

Abstract: A transmitter includes a bandwidth configuration unit configured to provide an increased system bandwidth corresponding to a bandwidth extension over multiple component carriers. Additionally, the transmitter also includes a transmit unit configured to employ the bandwidth extension.

Abstract: An apparatus for performing a Fast Fourier Transform (FFT) is provided. The apparatus comprises a reorder matrix, symmetrical butterflies, and a memory. The reorder matrix is configured to have a constant geometry, and the butterflies are coupled in parallel to the reorder matrix. The memory is also coupled to the reorder matrix and each butterfly. The reorder matrix, the butterflies, and the memory can then execute a split radix algorithm.

Abstract: An electronic communication device comprises a first transceiver capable of a bi-directional communication session on a first communication medium; a second transceiver capable of a bi-directional communication session on a second communication medium; and a control logic coupled to the first transceiver and the second transceiver, wherein the control logic is configured to receive, from the first transceiver, a first signal, and cause, in response to the first signal, data transmitted by the first transceiver on the first communication medium as part of a communication session to be transmitted instead by the second transceiver on the second communication medium while the first transceiver continues to receive data as part of the communication session.

Abstract: A method of forming stacked die devices includes attaching first semiconductor die onto a wafer to form a reconstituted wafer, and then bonding second semiconductor die onto the first semiconductor die to form a plurality of singulated stacked die devices on the wafer. A support tape is attached to a bottomside of the second semiconductor die. A dicing tape is attached to the wafer. The wafer is laser irradiated before or after attachment of the dicing tape at intended dicing lanes that align with gaps between the first semiconductor die to mechanically weaken the wafer at the intended dicing lanes, but not cut through the wafer. The dicing tape is pulled to cleave the wafer into a plurality of singulated portions to form a plurality of singulated stacked die devices attached to the singulated wafer portions by the dicing tape. The support tape is removed prior to cleaving.

Abstract: Semiconductor devices and fabrication methods are provided, in which metal transistor gates are provided for MOS transistors. A rare earth-rare earth alloy incorporated metal nitride layer is formed above a gate dielectric. This process provides adjustment of the gate electrode work function, thereby tuning the threshold voltage of the resulting NMOS transistors.

Abstract: Various apparatuses and methods for supplying an electrical current are disclosed herein. For example, some embodiments provide an apparatus including a current regulation switch connected in a current path between a power input and a current output. A current regulator is connected to the current regulation switch. The current regulator includes a current set terminal, and the current through the current regulation switch is proportional to the current through current set terminal. An impedance monitor is connected to the current set terminal.

Abstract: One method of making an electronic assembly includes mounting one electrical substrate on another electrical substrate with a face surface on the one substrate oriented transversely of a face surface of the other substrate. The method also includes inkjet printing on the face surfaces a conductive trace that connects an electrical contact on the one substrate with an electrical connector on the other substrate. An electronic assembly may include a first substrate having a generally flat surface with a first plurality of electrical contacts thereon; a second substrate having a generally flat surface with a second plurality of electrical contacts thereon, the surface of the second substrate extending transversely of the surface of said first substrate; and at least one continuous conductive ink trace electrically connecting at least one of the first plurality of electrical contacts with at least one of the second plurality of electrical contacts.

Abstract: A sensing arrangement and method a sense winding is used to provide a voltage which represents the voltage appearing across an in-circuit magnetic component. In a flyback phase, when the component is supplying the output, that voltage represents an output voltage and in a supply phase, the supply voltage. This arrangement provides a solution to the problem of the disparity in magnitude of sense winding output during the two phases by proving a pull-up resistor arranged to apply bias to the voltage measured, the pull-up being to a first level during the supply period and to a second value during the flyback period, the first and second levels being selected such that the voltage across the sense winding is scaled differently during the supply period and the flyback period. The invention is suitable for use in a transformer based flyback power converter in which the magnitude disparity problem may be exacerbated by a turns ratio.

Abstract: A user-heading determining system (10) for pedestrian use includes a multiple-axis accelerometer (110) having acceleration sensors; a device-heading sensor circuit (115) physically situated in a fixed relationship to the accelerometer (110); an electronic circuit (100) operable to generate signals representing components of acceleration sensed by the accelerometer (110) sensors, and to electronically process at least some part of the signals to produce an estimation of attitude of a user motion with respect to the accelerometer, and further to combine the attitude estimation (750, ?) with a device heading estimation (770, ?) responsive to the device-heading sensor circuit, to produce a user heading estimation (780); and an electronic display (190) responsive to the electronic circuit (100) to display information at least in part based on the user heading estimation. Other systems, circuits and processes are also disclosed.