Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. Clock signals CKT and CLKZ and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CKT and CLKN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, SS, SSN and PREN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.

Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. Clock signals CKT and CLKZ and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CKT and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, SS, SSN and PREN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.

Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. Clock signals CKT and CLKZ and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CKT and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, SS, SSN and PREN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.

Abstract: A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing test access to these individual cores via a test structure called a wrapper. The wrapper resides at the boundary of the core and provides a way to test the core and the interconnections between cores.—The test architecture enables each of the plural wrappers in the IC, including wrappers in cores embedded within other cores, with separate enable signals.

Abstract: A method of operating a user equipment device includes extracting at least one rank indicator (RI) from an uplink grant, and adapting a transmission rank in response to said RI. At least two transmit antennas are configured to transmit according to said transmission rank.

Abstract: An amplifier having an inverting input and a non-inverting input; a capacitor coupled to inverting input of the amplifier; an input voltage conveyance control circuit, having a first switch and a second switch, the first switch coupled to the capacitor, and the second switch coupled to the non-inverting input of the amplifier; a reference voltage conveyance control circuit having a third switch and a fourth switch, a shared node coupled between third switch and fourth switch, the fourth switch coupled to the non-inverting input of the amplifier; a fifth switch coupled to an output of the amplifier; a leakage control circuit having a sixth switch and seventh switch, the sixth switch coupled between the inverting amplifier input and the fifth switch, the seventh switch coupled to the sixth switch and the capacitor; and a first resistor coupled from the output of the amplifier to the first switch.

Abstract: A secure demand paging (SDP) system includes a dynamic random access memory (DRAM), a microprocessor having a secure internal memory and coupled to said DRAM, and a non-volatile memory storing a representation of operations accessible by the microprocessor. The stored representation of operations includes a coded physical representation of operations to configure an SDP space in the DRAM, to organize the SDP space into virtual machine contexts, to organize at least one of the virtual machine contexts into block book keeping blocks and book keeping spaces in the block book keeping blocks, and to execute a secure demand paging process between said secure internal memory and said DRAM.

Abstract: A contactless system is described in which energy is scavenged from an electromagnetic field provided by a proximate reader device. An embedded processor and a volatile memory circuit within a near field communication (NFC) controller are operated using the scavenged energy. Parameter data from the proximate reader device may be acquired while conducting a near field communication transaction. A non-volatile memory (NVRAM) server is coupled to the NFC controller and also operates using the scavenged energy. Parameter data may be stored within the NVRAM server by sending a command and the parameter data from the NFC controller to the NVRAM server. At the completion of the transaction, the electromagnet field may be removed and all parameter data stored within the NFC controller will be lost. However, the next time the electromagnetic field is applied, the NFC controller may retrieve the parameters from the NVRAM server by sending a command.

Abstract: A device is provided that includes a chip having a processor and wake-up logic. The device also includes power management circuitry coupled to the chip. The power management circuitry selectively provides a core power supply and an input/output (I/O) power supply to the chip. Even if the power management circuitry cuts off the core power supply to the chip, the wake-up logic detects and responds to wake-up events based on power provided by the I/O power supply.

Abstract: A packaged sensor MEMS (100) has a semiconductor chip (101) with a protected cavity (102) including a sensor (105), the cavity surrounded by solder bumps (130) attached to the chip terminals; further a leadframe with elongated and radially positioned leads (131), the central lead ends (131a) attached to the bumps. Insulating material (120) encapsulates chip and central lead ends, leaving the chip surface (101a) opposite the cavity and the peripheral lead ends (131b) un-encapsulated. The un-encapsulated peripheral lead ends are bent into cantilevers for attachment to a horizontal substrate (160), the cantilevers having a geometry to accommodate, under a force lying in the plane of the substrate, elastic bending and stretching beyond the limit of simple elongation based upon inherent material characteristics, especially when supported by lead portions with curved, toroidal, or multiple-bendings geometries.

Abstract: A light-emitting diode (LED) driver system includes a control circuit that provides a waveform for driving a power transistor to generate a regulated current through one or more LEDs, and an error amplifier that generates an output compensation signal based on a comparison of a desired regulated current and an actual regulated current through the one or more LEDs. The output compensation signal is used to set an output compensation voltage that sets the duty cycle of the waveform. The LED driver system further comprises a dimming control device configured during a dimming control mode to alternate between dimming-on time periods and dimming-off time periods, and a sample and hold switch having a first state for holding the output compensation voltage fixed during each dimming-off time period, and a second state for restoring the error amplifier to its previous dimming-on operating state upon returning to each subsequent dimming-on time period.

Abstract: One aspect of the present invention includes a light-emitting diode (LED) power supply system. The system includes an LED regulator configured to monitor at least one LED voltage associated with a respective at least one activated LED string and to generate an LED regulation voltage based on the at least one LED voltage relative to an LED power voltage that provides power to the at least one activated LED string. The system also includes a power converter configured to generate the LED power voltage and to regulate the LED power voltage based on the LED regulation voltage.

Abstract: A method of power saving for a wireless transceiver (FIGS. 1 and 2) is disclosed. The transceiver has an active power mode (504) and a reduced power mode (510). The transceiver is operated in the reduced power mode (510) and monitors transmissions from a remote wireless transmitter while in the reduced power mode. The transceiver identifies a transmission from the remote wireless transmitter by a transceiver identity included in the transmission (FIG. 6, UE identification). The transceiver transitions to the active power mode (512) in response to identifying the transmission.

Abstract: Coupling and interface circuits for powerline modems are disclosed. A powerline modem may be coupled to a low voltage (LV) line or a medium voltage (MV) line using a circuit that is designed to compensate for signal attenuation and loss that is created by the a LV/MV transformer and/or a MV coupler. In one embodiment, separate coupling transformers may be used by the modem for reception and transmission. In other embodiments, a capacitance is switched on the transmission line before the modem transmits to lower the line impedance.

Abstract: A method of reducing leakage current in a memory circuit is disclosed (FIG. 8A). The method includes connecting a first supply voltage terminal (VDD) to a bulk terminal of a transistor in an active mode of operation. The method further includes detecting a low power mode (SLEEP) of operation of the transistor and disconnecting the first supply voltage terminal from the bulk terminal in response to the step of detecting.

Abstract: Peak current in a switching converter is controlled using a closed loop to compensate for error caused by delay time in the switching transistor and control logic. A reference value is established that represents a target current value. A compensated reference value is derived from the reference value by the closed loop. A periodic inductor current is formed in the switching converter in response to the compensated reference value. An error signal is formed that is indicative of an amount of time the inductor current exceeds the target current value. The compensated reference value is dynamically adjusted by the compensation closed loop to minimize the error signal.

Abstract: A silicon nitrate layer (110) is formed over a transistor gate (40) and source and drain regions (70). The as-formed silicon nitride layer (110) comprises a first tensile stress and a high hydrogen concentration. The as-formed silicon nitride layer (110) is thermally annealed converting the first tensile stress into a second tensile stress that is larger than the first tensile stress. Following the thermal anneal, the hydrogen concentration in the silicon nitride layer (110) is greater than 12 atomic percent.

Abstract: A control circuit configured to control a switching power supply including a ramp generator configured to generate a triangular waveform. A comparator is configured to generate a series of pulse width modulated (PWM) pulses at a first frequency and to regulate the switching power supply. The ramp generator includes a capacitor, a charging current source configured to provide a charging current to charge the capacitor, and a discharging current source configured to provide a discharging current to discharge the capacitor. The ramp generator also includes a closed loop current balancing current source configured to balance the currents from the charging and discharging current sources to establish a substantially zero direct current (DC) bias across the capacitor. The controller also includes a multi-phase configuration to provide a stackable multi-channel architecture.

Abstract: A method of noise filtering of a digital video sequence is provided that includes computing a motion image for a frame, wherein the motion image includes a motion value for each pixel in the frame, and wherein the motion values are computed as differences between pixel values in a luminance component of the frame and corresponding pixel values in a luminance component of a reference frame, applying a first spatial noise filter to the motion image to obtain a final motion image, computing a blending factor image for the frame, wherein the blending factor image includes a blending factor for each pixel in the frame, and wherein the blending factors are computed based on corresponding motion values in the final motion image, generating a filtered frame, wherein the blending factors are applied to corresponding pixel values in the reference frame and the frame, and outputting the filtered frame.

Abstract: Communications systems and methods for transmitting communications between a charge system and an AC adapter are disclosed. In one embodiment, a communication system comprises an AC adapter disconnect switch that is switchable between coupling and decoupling an AC adapter DC output voltage to the charge system and a charge controller configured to modulate the AC adapter disconnect switch between coupling and decoupling to provide a communication signal to the AC adapter.